參數(shù)資料
型號(hào)： STE10/100E
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP128
封裝： 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, QFP-128
文件頁(yè)數(shù)： 42/66頁(yè)
文件大?。?/td> 396K
代理商： STE10/100E
47/66
STE10/100A
6.3.2 Transmit pre-fetch data flow
s
Transmit FIFO size=2K-byte
s
two packets in the FIFO at the same time
s
meet the transmit min. back-to-back
Figure 10. Transmit data flow of pre-fetch data
6.3.3 Transmit early interrupt Scheme
Figure 11. Transmit normal interrupt and early interrupt comparison
place the 1st packet data into host memory
issue transmit demand
FIFO-to-host memory operation (1st packet)
time
Transmit enable
place the 2nd packet data into host memory
check the next
packet
check point
FIFO-to-host memory operation (2nd packet)
transmit threshold
place the 3rd packet data into host memory
1st packet is
transmitted, check
the 3rd packet
FIFO-to-host memory operation (3rd packet)
IFG
check point
1st packet
2nd packet
: handled by driver
: handled by STE10/100A
Host to TX-FIFO Memory
Operation
Transmit data from FIFO to Media
Normal Interrupt after Transmit
Completed
Driver return buffer to upper layer
Early Interrupt after Host to TX-
FIFO Operation Completed
Driver return buffer to upper layer
The saved time when transmit
early interrupt is implemented
time
: handled by STE10/100A
: handled by driver
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