參數(shù)資料
型號(hào)： STE10/100E
廠商： STMICROELECTRONICS
元件分類(lèi)： 微控制器/微處理器
英文描述： 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP128
封裝： 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, QFP-128
文件頁(yè)數(shù)： 21/66頁(yè)
文件大小： 396K
代理商： STE10/100E
STE10/100A
28/66
5
PAUSE
Disable or enable the PAUSE function for flow control. The
default value of PAUSE is determined by the result of Auto-
Negotiation. The driver software can overwrite this bit to
enable or disable it after the Auto-Negotiation has completed.
0: PAUSE function is disabled.
1: PAUSE function is enabled
Depends
on the
result of
Auto-
Negotiation
R/W
4
RTE
Receive Threshold Enable.
1: the receive FIFO threshold is enabled.
0: disable the receive FIFO threshold selection in DRT (bits
3~2), and the receive threshold is set to the default 64 bytes.
0
R/W
3~2
DRT
Drain Receive Threshold
00: 32 bytes (8 DW)
01: 64 bytes (16 DW)
10: store-and -forward
11: reserved
01
R/W
1
SINT
Software interrupt.
0
R/W
0
ATUR
1: enable automatically transmit-underrun recovery.
0
R/W
CSR19(offset = 8ch) - PCIC, PCI bus performance counter
31~16
CLKCNT
The number of PCI clocks from read request asserted to
access completed. This PCI clock count is accumulated for all
the read command cycles from the last CSR19 read to the
current CSR19 read.
0RO*
15~8
---
reserved
7~0
DWCNT
The number of double words accessed by the last bus master.
This double word count is accumulated for all bus master data
transactions from the last CSR19 read to the current CSR19
read.
0RO*
RO* = Read only and cleared by reading.
CSR20 (offset = 90h) - PMCSR, Power Management Command and Status (The same register value mapping to
CR49-PMR1.)
31~16
---
reserved
15
PMES
PME_Status. This bit is set whenever the STE10/100A detects
a wake-up event, regardless of the state of the PME-En bit.
Writing a “1” to this bit will clear it, causing the STE10/100A to
deassert PME# (if so enabled). Writing a “0” has no effect.
0RO
14,13
DSCAL
Data_Scale. Indicates the scaling factor to be used when
interpreting the value of the Data register. This field is required
for any function that implements the Data register.
The STE10/100A does not support Data register and
Data_Scale.
00b
RO
12~9
DSEL
Data_Select. This four bit field is used to select which data is
to be reported through the Data register and Data_Scale field.
This field is required for any function that implements the Data
register.
The STE10/100A does not support Data_select.
0000b
RO
Table 6. Control/Status register description
Bit #
Name
Descriptions
Default Val
RW Type
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