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參數(shù)資料
| 型號(hào)： | STE10/100E |
| 廠商： | STMICROELECTRONICS |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP128 |
| 封裝： | 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, QFP-128 |
| 文件頁(yè)數(shù)： | 20/66頁(yè) |
| 文件大?。?/td> | 396K |
| 代理商： | STE10/100E |
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STE10/100A
CSR18(offset = 88h), CR - Command Register, bit31 to bit16 automatically recall from EEPROM
31
D3CS
D3cold power state wake up Support. If this bit is reset then bit
31 of PMR0 will be reset to ‘0’. If this bit is asserted and an
auxiliary power source is detected then bit 31 of PMR0 will be
set to ‘1’.
0
from
EEPROM
R/W
30-28
AUXCL
Aux. Current Load. These three bits report the maximum
3.3Vaux current requirements for STE10/100A chip. If bit 31 of
PMR0 is ‘1’, the default value is 111b, which means the
STE10/100A need 375 mA to support remote wake-up in
D3cold power state. Otherwise, the default value is 000b,
which means the STE10/100A does not support remote wake-
up from D3cold power state.
000b
from
EEPROM
R/W
27-24
---
Reserved
23
4LEDmode
_on
This bit is used to control the LED mode selection.
If this bit is reset, mode 1 (3 LEDs) is selected; the LEDs
definition is:
100/10 speed
Link/Activity
Full Duplex/Collision
If this bit is set, mode 2 (4 LEDs) is selected; the LEDs
definition is:
100 Link
10 Link
Activity
Full Duplex/Collision
0
from
EEPROM
R/W
22, 21
RFS
Receive FIFO size control
11: 1K bytes
10: 2K bytes
01,00: reserved
10
from
EEPROM
R/W
20
---
Reserved
19
PM
Power Management. Enables the STE10/100A Power
Management abilities. When this bit is set into “0” the STE10/
100A will set the Cap_Ptr register to zero, indicating no PCI
compliant power management capabilities. The value of this
bit will be mapped to NC (CR1 bit 20). In PCI Power
Management mode, the Wake Up Frames include “Magic
Packet”, “Unicast”, and “Muliticast”.
X
from
EEPROM
RO
18
WOL
Wake on LAN mode enable. When this bit is set to ‘1’, then the
STE10/100A enters Wake On LAN mode and enters the sleep
state.
Once the STE10/100A enters the sleep state, it remains there
until: the Wake Up event occurs, the WOL bit is cleared, or a
reset (software or hardware) happens.
In Wake On LAN mode the Wake-Up frame is “Magic Packet”
only.
X
from
EEPROM
R/W
17~7
---
Reserved
6
RWP
Reset Wake-up Pattern Data Register Pointer
0
R/W
Table 6. Control/Status register description
Bit #
Name
Descriptions
Default Val
RW Type
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