參數(shù)資料
型號(hào)： SST38VF166-70-4C-EK
廠商： SILICON STORAGE TECHNOLOGY INC
元件分類： PROM
英文描述： RECTIFIER BRIDGE 4A 600V 150A-ifsm 1V-vf 5uA-ir GBU 20/TUBE
中文描述： 1M X 16 FLASH 2.7V PROM, 70 ns, PDSO48
封裝： 12 X 20 MM, TSOP-48
文件頁(yè)數(shù)： 6/50頁(yè)
文件大?。?/td> 691K
代理商： SST38VF166-70-4C-EK
6
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
The requirements for JEDEC compliant SDP are in byte
format. The SST38VF166 is organized by word; therefore,
the contents of DQ
8
to DQ
15
are
“
Don
’
t Care
”
during any
SDP (3-word or 6-word) command sequence.
During the SDP load command sequence, the SDP load
cycle is suspended when WE# is high. This means a read
may occur to any other bank during the SDP load
sequence.
The SDP load sequence is bank specific, i.e., the same
BE# must be low for each bus cycle. If the command
sequence is aborted, e.g., a different BE# is brought low
(except for Read operation with WE# high), an incorrect
address is loaded, or incorrect data is loaded, the device
will return to the Read mode within T
RC
of execution of the
load error.
Concurrent Read and Write Operations
The SST38VF166 provides the unique benefit of being
able to read any bank, while simultaneously writing, eras-
ing, or programming one other bank. This allows data alter-
ation code to be executed from one bank, while altering the
data in another bank. The following table lists all valid
states.
Note:
For the purposes of this table, write means to Word-Write;
Block-, Sector-, or Chip-Erase; or Word-Program as applica-
ble to the appropriate bank.
SST does not recommend that any two of the bank enable
signals BE#1, BE#2 or BE#3 be simultaneously asserted.
The device will ignore all SDP commands and toggling of
WE# when an Erase, Program, or Write operation is in
progress. Note, both Product Identification and the Com-
mon Flash Interface entry commands use SDP; therefore,
these commands will also be ignored while an Erase, Pro-
gram, or Write operation is in progress.
Product Identification
The product identification mode identifies the device manu-
facturer as SST and provides a code to identify each bank.
The manufacturer ID is the same for each bank; however,
each bank has a separate device ID. Each bank is individu-
ally accessed using the applicable BE# and a software
command. Users may wish to use the device ID operation
to identify the write algorithm requirements for each bank.
For details, see Table 6 or 7 for software operation and Fig-
ures 27, 28, or 29 for timing waveforms.
Device IDs are unique to each bank. Should a chip ID be
required, any of the bank IDs may be used as the chip ID.
While in the read software ID mode or CFI mode, no other
operation is allowed until after exiting these modes.
Product Identification Mode Exit
In order to return to the standard Read mode, the Product
Identification mode must be exited. Exit is accomplished by
issuing the Software ID exit command, which returns the
device to normal operation. This command may also be
used to reset the device to the Read mode after any inad-
vertent transient condition that apparently causes the
device to behave abnormally, e.g., not read correctly. For
details, see Table 6 or 7 for software operation and Figures
30, 31, or 32 for timing waveforms.
TABLE
1: C
ONCURRENT
R
EAD
/W
RITE
S
TATE
Flash Bank 1
Read
Read
Write
No Operation
Write
No Operation
Flash Bank 2
No Operation
Write
Read
Read
No Operation
Write
E
2
Bank
Write
No Operation
No Operation
Write
Read
Read
T1.0 327
TABLE
2: P
RODUCT
I
DENTIFICATION
Address
0000H
Data
00BFH
Manufacturer
’
s ID
Device ID
Flash Bank 1
Flash Bank 2
E
2
Bank
0001H
0001H
0001H
2791H
2792H
2793H
T2.1 327
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SST38VF6401-90-5C-EKE 功能描述:閃存 64M (4Mx16) 90ns 2.7-3.6V Commercial RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲(chǔ)類型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類型: 接口類型:SPI 訪問(wèn)時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel
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