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參數(shù)資料
| 型號： | SST38VF166-70-4C-EK |
| 廠商： | SILICON STORAGE TECHNOLOGY INC |
| 元件分類： | PROM |
| 英文描述： | RECTIFIER BRIDGE 4A 600V 150A-ifsm 1V-vf 5uA-ir GBU 20/TUBE |
| 中文描述： | 1M X 16 FLASH 2.7V PROM, 70 ns, PDSO48 |
| 封裝： | 12 X 20 MM, TSOP-48 |
| 文件頁數(shù)： | 2/50頁 |
| 文件大?。?/td> | 691K |
| 代理商： | SST38VF166-70-4C-EK |
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2
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
Flash bank, BE#2 selects the second Flash bank, BE#3
selects the E
2
bank. WE# is used with SDP to control the
Write or Erase and Program operation in each memory
bank.
The SST38VF166 provides the added functionality of
being able to simultaneously read from one memory bank
while writing, erasing, or programming to one other mem-
ory bank. Once the internally controlled Write, Erase, or
Program cycle in a memory bank has commenced, a differ-
ent memory bank can be accessed for read. Also, once
WE# and the applicable BE# are high during the SDP load
sequence, a different bank may be accessed to read. If
multiple bank enables are asserted simultaneously, the out-
puts will tri-state and no new memory operations can be
initiated. Only one bank may be written, erased, or pro-
grammed at any given time. The device ID and Common
Flash Interface (CFI) functions cannot be accessed while
any bank is writing, erasing, or programming.
The
Auto Low Power Mode
automatically puts the device
in a near standby mode after data has been accessed with
a valid Read operation. This reduces the I
DD
active read
current from typically 15mA to typically 3μA. The Auto Low
Power mode reduces the typical I
DD
active read current to
the range of 1mA/MHz of Read cycle time. The device exits
the
Auto Low Power Mode
with any address transition or
control signal transition used to initiate another Read cycle,
with no access time penalty.
Flash Bank Read
The Read operation of the SST38VF166 Flash Bank is
controlled by BE#1 or BE#2 and OE#, a bank enable and
output enable both have to be low for the system to obtain
data from the outputs. BE#1 is used for Flash bank 1
selection. When BE#1 is high, the Flash bank 1 is dese-
lected. BE#2 is used for Flash bank 2 selection. When
BE#2 is high, the Flash bank 2 is deselected. OE# is the
output control and is used to gate data from the output
pins. The data bus is in high impedance state when OE#
is high. Refer to the timing waveforms for further details
(Figure 2 or 3).
E
2
Bank Read
The Read operation of the E
2
bank is controlled by BE#3
and OE#, both have to be low for the system to obtain data
from the outputs. BE#3 is used for E
2
bank selection. When
BE#3 is high, the E
2
bank is deselected. OE# is the output
control and is used to gate data from the output pins. The
data bus is in high impedance state when OE# is high.
Refer to the timing waveforms for further details (Figure 4).
Write Modes
The SST38VF166 device has separate Write modes for
the E
2
bank and Flash banks. The conventional E
2
PROM
Word-Write with internally timed automatic Erase before
Program is the most convenient and easy method for the
user to alter data in the E
2
bank with the Word-Write opera-
tion, the word being written is the only word that is altered.
Bank- or Sector-Erase plus Word-Program operations may
also be used for the E
2
bank. For both banks of the Flash
array, the SST38VF166 offers Bank-, Block-, and Sector-
Erase plus Word-Program operations.
Write
All Write operations are initiated by first issuing the Soft-
ware Data Protect (SDP) entry sequence for Bank-, Block-,
or Sector-Erase then Word-Program in the selected Flash
bank; or for Word-Write or for Sector-Erase and Word-Pro-
gram in the E
2
bank. Word-Write, Word-Program, and all
Erase commands have a fixed duration, that will not vary
over the life of the device, i.e., are independent of the num-
ber of Erase/Program cycles endured.
Either Flash bank may be read during the internally con-
trolled E
2
bank Write cycle, e.g., the Flash bank may be
accessed to fetch instructions or data when the E
2
bank is
being written, erased, or programmed. Additionally, the
alternate Flash bank may be read while erasing or pro-
gramming the other Flash or E
2
bank. At any given time,
only one bank may be performing a Write operation, during
that time any other bank is available for read.
The Write Status command may be used to determine if
any bank is being written, at any given time. This may be
required if the system does not use a timer or does not
monitor toggle bit or data# polling when writing a specific
bank. In order to implement the Write Status command,
address 5XXXH in the E
2
bank address space is reserved.
This address is outside the normal address space of the E
2
bank; therefore, will not interfere with normal reading within
the E
2
bank address space.
The device is always in the Software Data Protected mode
for all Write operations in both the Flash bank and E
2
bank.
Write operations are controlled by toggling WE# or BE#.
The falling edge of WE# or BE#, whichever occurs last,
latches the address. The rising edge of WE# or BE#,
whichever occurs last, latches the data and initiates the
Erase, Program, or Write cycle.
The SDP Erase, Program, or Write commands are all BE#
specific. Whichever BE# is used for the first SDP bus cycle
(except for Read operation with WE# high), that BE# must
be used for all subsequent SDP bus cycles, for the com-
mand to be executed. If a different BE# is pulsed during a
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