參數(shù)資料
型號: SST38VF166-70-4C-EK
廠商: SILICON STORAGE TECHNOLOGY INC
元件分類: PROM
英文描述: RECTIFIER BRIDGE 4A 600V 150A-ifsm 1V-vf 5uA-ir GBU 20/TUBE
中文描述: 1M X 16 FLASH 2.7V PROM, 70 ns, PDSO48
封裝: 12 X 20 MM, TSOP-48
文件頁數(shù): 5/50頁
文件大?。?/td> 691K
代理商: SST38VF166-70-4C-EK
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
5
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
be no issue when recovering from the system reset. See
Table 6 or 7 for the specific codes and Figure 40 for a timing
waveform.
There is no provision to abort an Erase, Program, or Write
operation, once initiated. For the SST SuperFlash technol-
ogy, the associated Erase, Program, and Write times are
so fast, relative to system reset times, there is no value in
aborting the operation. Note, reads can always occur from
any bank not performing an Erase, Program, or Write oper-
ation.
Should the system reset, while a Block- or Sector-Erase or
Word-Program is in progress in the bank where the boot
code is stored, the system must wait for the completion of
the operation before reading that bank. Since the maxi-
mum time the system would have to wait is 25 ms (for a
Block-Erase), the system ability to read the boot code
would not be affected.
Data# Polling (DQ
7
) - Flash Bank
When the SST38VF166 is in the internal Flash bank Pro-
gram cycle, any attempt to read DQ
7
of the last word
loaded during the Flash bank Word Load cycle will receive
the complement of the true data. Once the Write cycle is
completed, DQ
7
will show true data. The device is then
ready for the next operation. See Figure 21 or 22 for the
Flash bank Data Polling timing waveforms and Figure 51
for a flowchart.
Data# Polling (DQ
7
) - E
2
Bank
When the SST38VF166 is in the internal E
2
bank Write
cycle, any attempt to read DQ
7
of the last word loaded dur-
ing the E
2
bank Word Load cycle will receive the comple-
ment of the true data. Once the Write cycle is completed,
DQ
7
will show true data. The device is then ready for the
next operation. See Figure 23 for E
2
bank Data Polling tim-
ing waveforms and Figure 51 for a flowchart.
Toggle Bit (DQ
6
) - Flash Bank
During the Flash bank internal Write cycle, any consecutive
attempts to read DQ
6
will produce alternating 0s and 1s,
i.e. toggling between 0 and 1. When the Write cycle is com-
pleted, the toggling will stop. The device is then ready for
the next operation. See Figure 24 or 25 for Flash bank Tog-
gle Bit timing waveforms and Figure 51 for a flowchart.
Toggle Bit (DQ
6
) - E
2
Bank
During the E
2
bank internal Write cycle, any consecutive
attempts to read DQ
6
will produce alternating 0s and 1s,
i.e. toggling between 0 and 1. When the Write cycle is com-
pleted, the toggling will stop. The device is then ready for
the next operation. See Figure 26 for E
2
bank Toggle Bit
timing waveforms and Figure 51 for a flowchart.
Data Protection
The SST38VF166 provides both hardware and software
features to protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# pulse of less than 5 ns will
not initiate a Write cycle.
V
DD
Power Up/Down Detection: The Write operation is
inhibited when V
DD
is less than 1.5 volts.
Write Inhibit Mode: Forcing OE# low, BE#1 and BE#2 high,
or WE# high will inhibit the Write operation to the Flash
bank. Forcing OE# low, BE#3 high, or WE# high will inhibit
the Write operation to the E
2
bank. This prevents inadvert-
ent writes during power-up or power-down.
A One Time Programmable E
2
Sector
The first sector of the E
2
bank offers the option of OTP
(One Time Programmable) prevention of write for the first
sector, i.e., addresses A
5
to A
13
are
0
(0000H to 001FH).
Once the OTP software instruction is executed, no Write,
Erase, or Program operation can be performed on these 32
words. This is permanent and non-reversible. Additionally, if
the OTP prevention is enabled, the Bank-Erase for the E
2
bank will not function. See Table 7 for specific codes and
Figure 39 for a timing waveform.
Software Data Protection (SDP)
The SST38VF166 provides the JEDEC approved Software
Data Protection scheme as a requirement for initiating a
Write, Erase, or Program operation. With this scheme, any
Write operation requires the inclusion of a series of three
word-load operations to precede the Word-Write or Word-
Program operation. The three-word load sequence is used
to initiate the Write or Program cycle, providing optimal pro-
tection from inadvertent Write operations, e.g., during the
system power-up or power-down. The six-word sequence
is required to initiate any Bank-, Block-, or Sector-Erase
operation.
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