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參數資料
| 型號： | SP37E760-MD |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 外設及接口 |
| 英文描述： | 3.3 V I/O CONTROLLER FOR EMBEDDED APPLICATIONS |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數： | 71/78頁 |
| 文件大?。?/td> | 510K |
| 代理商： | SP37E760-MD |
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SMSC DS – SP37E760
Page 71
Rev. 04/13/2001
9.3.2
9.3.2.1
The standard parallel port is run at or near the peak 500 Kbps allowed in the forward direction using DMA. The state
machine does not examine nAck and begins the next transfer based on Busy. Refer to FIGURE 14.
9.3.2.2
ECP Parallel Port Timing
The timing is designed to allow operation at approximately 2.0Mbytes/sec over a 15ft cable. If a shorter cable is used
then the bandwidth will increase.
9.3.2.3
Forward-Idle
When the host has no data to send it keeps HostClk (nStrobe) high and the peripheral will leave PeriphClk (Busy)
low.
PARALLEL PORT ECP TIMING
Parallel Port FIFO (Mode 101)
t20
t19
t11
t15
t22
t13
t12
t3
t8
t10
t5
t4
t23
t2
t21
AX
nIOR
SD<7:0>
IOCHRDY
nWRITE
PD<7:0>
nDATASTB
nADDRSTB
nWAIT
t2
t3
t4
t5
t8
t10
t11
t12
t13
t15
t19
t20
t21
t22
t23
nIOR Deasserted to Command Deasserted
nWAIT Asserted to IOCHRDY Deasserted
Command Deasserted to PDATA Hi-Z
Command Asserted to PDATA Valid
nIOR Asserted to IOCHRDY Asserted
nWAIT Deasserted to nIOCHRDY Deasserted
nIOCHRDY Deasserted to nIOR Deasserted
nIOR Deasserted to SDATA High-Z (Hold Time)
PData Valid to SDATA Valid
Time Out
Ax Valid to nIOR Asserted
nIOR Deasserted to Ax Invalid
Command Deasserted to nWAIT Deasserted
nIOR Deasserted to nIOW or nIOR Asserted
nIOR Asserted to Command Asserted
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns
ns
ns
ns
50
40
24
50
40
40
12
55
Parameter
min
max
units
0
0
0
0
0
10
40
10
0
40
Notes
NOTE:
1. nWRITE is controlled by setting the PDIR bit to "1" in the control register before
performing an EPP Read.
FIGURE 13 - EPP 1.7 DATA OR ADDRESS READ CYCLE
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