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參數(shù)資料
| 型號： | SP37E760-MD |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | 3.3 V I/O CONTROLLER FOR EMBEDDED APPLICATIONS |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 24/78頁 |
| 文件大?。?/td> | 510K |
| 代理商： | SP37E760-MD |
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1. Bit 0=1 as long as there is one byte in the RCVR FIFO.
2. Bits 1 to 4 specify which error(s) have occurred. Character error status is handled the same way as when in
the interrupt mode, the IIR is not affected since EIR bit 2=0.
3. Bit 5 indicates when the XMIT FIFO is empty.
4. Bit 6 indicates that both the XMIT FIFO and shift register are empty.
5. Bit 7 indicates whether there are any errors in the RCVR FIFO.
There is no trigger level reached or time-out condition indicated in the FIFO Polled Mode, however, the RCVR and
XMIT FIFOs are still fully capable of holding characters.
Table 11 - Individual UART Channel Register Summary
REGISTER
ADDRESS*
REGISTER NAME
SYMBOL
ADDR = 0
DLAB = 0
(Read Only)
ADDR = 0
DLAB = 0
Register (Write Only)
ADDR = 1
DLAB = 0
SMSC DS – SP37E760
Page 24
Rev. 04/13/2001
REGISTER
BIT 0
BIT 1
Receive Buffer Register
RBR
Data Bit 0 (Note
1)
Data Bit 1
Transmitter Holding
THR
Data Bit 0
Data Bit 1
Interrupt Enable Register
IER
Enable Received
Data Available
Interrupt (ERDAI)
Enable Transmitter
Holding Register
Empty Interrupt
(ETHREI)
Interrupt ID Bit
ADDR = 2
ADDR = 2
Interrupt Ident. Register
(Read Only)
IIR
”0” if Interrupt
Pending
FIFO Control Register
(Write Only)
Line Control Register
FCR
FIFO Enable
RCVR FIFO Reset
ADDR = 3
LCR
Word Length
Select Bit 0
(WLS0)
Data Terminal
Ready (DTR)
Word Length
Select Bit 1
(WLS1)
Request to Send
(RTS)
ADDR = 4
ADDR = 5
ADDR = 6
ADDR = 7
ADDR = 0
DLAB = 1
ADDR = 1
DLAB = 1
MODEM Control Register
MCR
Line Status Register
MODEM Status Register
LSR
MSR
Data Ready (DR)
Delta Clear to
Send (DCTS)
Overrun Error (OE)
Delta Data Set
Ready (DDSR)
Scratch Register (Note 4)
Divisor Latch (LS)
SCR
DDL
Bit 0
Bit 0
Bit 1
Bit 1
Divisor Latch (MS)
DLM
Bit 8
Bit 9
*DLAB is Bit 7 of the Line Control Register (ADDR = 3).
Note 1:
Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
Note 2:
When operating in the XT mode, this bit will be set any time that the transmitter shift register is empty.
Table 12 - Individual UART Channel Register Summary Continued
BIT 3
BIT 4
Data Bit 3
Data Bit 4
BIT 2
BIT 5
BIT 6
BIT 7
Data Bit 2
Data Bit 2
Enable
Receiver Line
Status
Interrupt
(ELSI)
Data Bit 5
Data Bit 6
Data Bit 7
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
Enable
MODEM
Status
Interrupt
(EMSI)
0
0
0
0
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