- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄365670 > SP37E760-MD (STANDARD MICROSYSTEMS CORP) 3.3 V I/O CONTROLLER FOR EMBEDDED APPLICATIONS PDF資料下載
參數(shù)資料
| 型號： | SP37E760-MD |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 外設及接口 |
| 英文描述： | 3.3 V I/O CONTROLLER FOR EMBEDDED APPLICATIONS |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 37/78頁 |
| 文件大?。?/td> | 510K |
| 代理商： | SP37E760-MD |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁當前第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁
Bytes written or DMAed from the system to this FIFO are transmitted by a hardware handshake to the peripheral
using the standard parallel port protocol. Transfers to the FIFO are byte aligned. This mode is only defined for the
forward direction.
5.4.4.5
ecpDFifo (ECP Data FIFO)
ADDRESS OFFSET = 400H
Mode = 011
Bytes written or DMAed from the system to this FIFO, when the direction bit is 0, are transmitted by a hardware
handshake to the peripheral using the ECP parallel port protocol. Transfers to the FIFO are byte aligned.
Data bytes from the peripheral are read under automatic hardware handshake from ECP into this FIFO when the
direction bit is 1. Reads or DMAs from the FIFO will return bytes of ECP data to the system.
5.4.4.6
tFifo (Test FIFO Mode)
ADDRESS OFFSET = 400H
Mode = 110
Data bytes may be read, written or DMAed to or from the system to this FIFO in any direction.
Data in the tFIFO will not be transmitted to the to the parallel port lines using a hardware protocol handshake.
However, data in the tFIFO may be displayed on the parallel port data lines.
The tFIFO will not stall when overwritten or underrun. If an attempt is made to write data to a full tFIFO, the new data
is not accepted into the tFIFO. If an attempt is made to read data from an empty tFIFO, the last data byte is re-read
again. The full and empty bits must always keep track of the correct FIFO state. The tFIFO will transfer data at the
maximum ISA rate so that software may generate performance metrics.
The FIFO size and interrupt threshold can be determined by writing bytes to the FIFO and checking the full and
serviceIntr bits.
The writeIntrThreshold can be determined by starting with a full tFIFO, setting the direction bit to 0 and emptying it a
byte at a time until serviceIntr is set. This may generate a spurious interrupt, but will indicate that the threshold has
been reached.
The readIntrThreshold can be determined by setting the direction bit to 1 and filling the empty tFIFO a byte at a time
until
serviceIntr
is set. This may generate a spurious interrupt, but will indicate that the threshold has been reached.
Data bytes are always read from the head of tFIFO regardless of the value of the direction bit. For example if 44h,
33h, 22h is written to the FIFO, then reading the tFIFO will return 44h, 33h, 22h in the same order as was written.
5.4.4.7
cnfgA (Configuration Register A)
ADDRESS OFFSET = 400H
Mode = 111
This register is a read only register. When read, 10H is returned. This indicates to the system that this is an 8-bit
implementation. (PWord = 1 byte)
5.4.4.8
cnfgB (Configuration Register B)
ADDRESS OFFSET = 401H
Mode = 111
SMSC DS – SP37E760
Page 37
Rev. 04/13/2001
5.4.4.8.1
This bit is read only. During a read it is a low level. This means that this chip does not support hardware RLE
compression. It does support hardware de-compression!
BIT 7 compress
5.4.4.8.2
Returns the value on the ISA iRq line to determine possible conflicts.
BIT 6 intrValue
5.4.4.8.3
During a read are a low level. These bits cannot be written.
BITS 5:0 Reserved
相關PDF資料 |
PDF描述 |
|---|---|
| SP37E760 | 3.3 V I/O CONTROLLER FOR EMBEDDED APPLICATIONS |
| SP37E760-MC | 3.3 V I/O CONTROLLER FOR EMBEDDED APPLICATIONS |
| SP8720 | ECL two-modulus divider, with ECL10K compatible outputs |
| SP8720ADG | ECL two-modulus divider, with ECL10K compatible outputs |
| SP8720BDG | ECL two-modulus divider, with ECL10K compatible outputs |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SP37E760-MT | 功能描述:輸入/輸出控制器接口集成電路 Super I/O Controller RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| SP37R0FL | 制造商:TE Connectivity 功能描述:SP3 7R0 1% LOOSEFixed Resistor |
| SP38 | 制造商:BES 功能描述:3/8" x 6" Spade Bit 制造商:BES MANUFACTURING 功能描述:SPADE BIT 3/8 X 6 INCH |
| SP380 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NOR GATES |
| SP38003 | 制造商:SIPAT 制造商全稱:SIPAT 功能描述:SAW Filter Electrical Characteristic |
發(fā)布緊急采購，3分鐘左右您將得到回復。