
SMSC DS – SP37E760
Page 3
Rev. 04/13/2001
TABLE OF CONTENTS
1
PIN CONFIGURATIONS.......................................................................................................................6
2
PIN DESCRIPTION ...............................................................................................................................8
2.1
2.2
2.3
B
UFFER
T
YPE
P
ER
P
IN
......................................................................................................................8
B
UFFER
T
YPE
S
UMMARY
.................................................................................................................12
O
UTPUT
D
RIVERS
...........................................................................................................................12
3
FUNCTIONAL DESCRIPTION............................................................................................................14
3.1
H
OST
P
ROCESSOR
I
NTERFACE
........................................................................................................14
4
SERIAL PORT (UART) .......................................................................................................................15
4.1
R
EGISTER
D
ESCRIPTION
.................................................................................................................15
RECEIVE BUFFER REGISTER (RB)...................................................................................15
TRANSMIT BUFFER REGISTER (TB).................................................................................15
INTERRUPT ENABLE REGISTER (IER)..............................................................................15
INTERRUPT IDENTIFICATION REGISTER (IIR) ................................................................16
FIFO CONTROL REGISTER (FCR).....................................................................................17
LINE CONTROL REGISTER (LCR)......................................................................................18
MODEM CONTROL REGISTER (MCR)...............................................................................19
LINE STATUS REGISTER (LSR) .........................................................................................20
MODEM STATUS REGISTER (MSR) ..................................................................................21
4.1.10
SCRATCHPAD REGISTER (SCR).......................................................................................21
4.1.11
PROGRAMMABLE BAUD RATE GENERATOR DIVISOR LATCHES................................21
4.1.12
The Affects of RESET on the UART Registers.....................................................................22
4.2
FIFO
I
NTERRUPT
M
ODE
O
PERATION
................................................................................................23
4.3
FIFO
P
OLLED
M
ODE
O
PERATION
....................................................................................................23
4.4
N
OTES
O
N
S
ERIAL
P
ORT
FIFO
M
ODE
O
PERATION
...........................................................................25
4.4.1
GENERAL .............................................................................................................................25
4.4.2
TX AND RX FIFO OPERATION............................................................................................25
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.6
4.1.7
4.1.8
4.1.9
5
PARALLEL PORT...............................................................................................................................27
5.1
IBM
XT/AT
COMPATIBLE,
BI-DIRECTIONAL
AND
EPP
MODES..............................................28
DATA PORT..........................................................................................................................28
STATUS PORT .....................................................................................................................28
CONTROL PORT..................................................................................................................29
EPP ADDRESS PORT..........................................................................................................29
EPP DATA PORT 0...............................................................................................................29
EPP DATA PORT 1...............................................................................................................29
EPP DATA PORT 2...............................................................................................................30
EPP DATA PORT 3...............................................................................................................30
EPP
1.9
OPERATION...................................................................................................................30
Software Constraints.............................................................................................................30
EPP 1.9 Write........................................................................................................................30
EPP 1.9 Read........................................................................................................................31
EPP
1.7
OPERATION...................................................................................................................31
Software Constraints.............................................................................................................31
EPP 1.7 Write........................................................................................................................31
EPP 1.7 Read........................................................................................................................32
EXTENDED
CAPABILITIES
PARALLEL
PORT...........................................................................33
Vocabulary ............................................................................................................................33
ISA IMPLEMENTATION STANDARD...................................................................................34
Description ............................................................................................................................34
Register Definitions...............................................................................................................35
OPERATION .........................................................................................................................39
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
5.1.8
5.2
5.2.1
5.2.2
5.2.3
5.3
5.3.1
5.3.2
5.3.3
5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5