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參數(shù)資料
| 型號： | SP37E760-MD |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | 3.3 V I/O CONTROLLER FOR EMBEDDED APPLICATIONS |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 43/78頁 |
| 文件大小： | 510K |
| 代理商： | SP37E760-MD |
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SMSC DS – SP37E760
Page 43
Rev. 04/13/2001
6
Power management is provided for the following SP37E760 logical devices: UART1, UART2 and the Parallel Port.
For each logical device two types of power management are provided; direct powerdown and auto powerdown.
Direct powerdown is controlled by the powerdown bits in the configuration registers. One bit is provided for each
logical device. Auto powerdown can be enabled for each logical device by setting the Auto Powerdown Enable bits in
the configuration registers. In addition, a chip-level hardware powerdown function has been provided through the
PWRGD pin. Refer to Table 1 and to other descriptions of the PWRGD function, for example section
CONFIGURATION, for more information.
AUTO POWER MANAGEMENT
6.1 Pin Behavior
The SP37E760 is specifically designed for portable PC systems where power conservation is a primary concern.
Consequently, the behavior of the device pins during powerdown are very important.
6.1.1
Table 22 gives the state of the system interface pins in the powerdown state. Pins unaffected by the powerdown are
labeled “Unchanged”. Input pins are “Disabled” to prevent them from causing currents internal to the SP37E760
when they have indeterminate input values.
Table 22 - State of System Pins in Auto Powerdown
SYSTEM PINS
STATE IN AUTO POWERDOWN
Input Pins
IOR
IOW
A[0:9]
D[0:7]
RESET
IDENT
DACK
TC
Output Pins
FINTR
DB[0:7]
FDRQ
SYSTEM INTERFACE PINS
Unchanged
Unchanged
Unchanged
Unchanged
Unchanged
Unchanged
Unchanged
Unchanged
Unchanged (low)
Unchanged
Unchanged (low)
6.2 UART Power Management
Direct UART power management is controlled by the UART1 and UART2 Power Down bits in Configuration Register
2. Refer to section
CR02 on page 49 for more information.
UART Auto Power Management is enabled by the UART 1 and UART 2 Enable bits in Configuration Register 7 (see
section CR07 on page 51). When set, these bits enable the following auto power management features:
1. The transmitter enters auto powerdown when the transmit buffer and transmit shift register are empty.
2. The receiver enters powerdown when the following conditions are all met:
Receive FIFO is empty
The receiver is waiting for a start bit.
Note:
While in the powerdown state, the Ring Indicator interrupts are still valid and are activated when the RI
inputs change.
The UART transmitters exit the powerdown state on a write to the XMIT buffer. The UART receivers exit the auto
powerdown state when RXDx changes state.
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