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參數(shù)資料
| 型號： | SiI3531ACNU |
| 廠商： | Silicon Image, Inc. |
| 英文描述： | PCI Express to Serial ATA Controller |
| 中文描述： | PCI Express到串行ATA控制器 |
| 文件頁數(shù)： | 76/81頁 |
| 文件大?。?/td> | 553K |
| 代理商： | SII3531ACNU |
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PCI Express to Serial ATA Controller
Data Sheet
6.3.22 SError
Address Offset: 1F08
H
Access Type: Read/Write 1 Clear
Reset Value: 0x0000_0000
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0208-C
76
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
R R R R R
X F T S H C D B W
I
N
R
R
R
R
E
P
C
T
R
R R R R
R
M
I
DIAG
ERR
This register is the SError register as defined by the Serial ATA specification (section 10.1.2).
Bit [31:16]
: DIAG (R/W1C) – This field contains bits defined as shown in the following table. Writing a 1 to the
register bit clears the B, C, F, N, H, W, and X bits. Writing a 1 to the corresponding bits in the Port Interrupt
Status register also clears the F, N, W, and X bits. The B, C, and H bits operate independently of the
corresponding error counter registers; if the error counters are used, these bits should be ignored.
Bit
Definition
Description
B
C
D
10b to 8b decode error
CRC error
Disparity error
Latched decode error or disparity error from the Serial ATA PHY
Latched CRC error from the Serial ATA PHY
N/A, always 0; this error condition is combined with the decode
error and reported as B error
Latched Unrecognized FIS error from the Serial ATA Link
N/A, always 0
Indicates a change in the status of the Serial ATA PHY
Latched Handshake error from the Serial ATA PHY
Always 0
N/A, always 0
N/A, always 0
Latched ComWake status from the Serial ATA PHY
Latched ComInit status from the Serial ATA PHY
F
I
N
H
R
S
T
W
X
Unrecognized FIS type
PHY Internal error
PHYRDY change
Handshake error
Reserved
Link Sequence error
Transport state transition error
ComWake
Device Exchanged
Table 6-10 SError Register Bits (DIAG Field)
Bit [15:00]
: ERR – This field is not implemented; all bits are always 0.
6.3.23 SActive
Address Offset: 1F0C
H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Active bits
This register provides indirect access of the Port Device QActive registers (see section 6.3.18 for description). It contains
the Active bits used to determine the activity of native queued commands for the selected Port Multiplier port (selection in
SControl). A one in any bit position indicates that the corresponding command is still active in the device.
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