參數(shù)資料
型號(hào)： SiI3531ACNU
廠商： Silicon Image, Inc.
英文描述： PCI Express to Serial ATA Controller
中文描述： PCI Express到串行ATA控制器
文件頁(yè)數(shù)： 68/81頁(yè)
文件大小： 553K
代理商： SII3531ACNU
PCI Express to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0208-C
68
Table 6-8 Command Error Codes
Error Name
Code
Description
The ERR bit was set in a "register - device to host" FIS received from the
device. The task file registers are written back to PRB slot for host scrutiny.
The ERR bit was set in a "set device bits" FIS received from the device.
The SiI3531A detected an error during command execution that was not
reported by the device upon command completion.
The SiI3531A was unable to send the Initial command FIS for a command.
This can occur if a low-level link error occurs during command transmission.
The SiI3531A detected an inconsistency in protocol. Any departure from
standard Serial ATA protocol that causes indecision in the internal sequencers
will cause this error.
A Data FIS was received when a write data protocol was specified or a DMA
Activate FIS was received when a read data protocol was specified.
While transferring data from the SiI3531A to a device, the end of the Scatter
Gather list was encountered before the entire transfer was completed. The
device is requesting additional data but there is no Scatter Gather Entry to
define the source of data.
While transferring data from a device to the SiI3531A, the end of the Scatter
Gather list was encountered before the entire transfer was completed. Data
was received from the device but there is no Scatter Gather Entry to define
where the data should be deposited.
During the first PIO setup of Packet command, the data direction bit was
invalid, indicating a transfer from device to host.
A requested Scatter Gather Table not aligned on a quadword boundary. All
addresses defining Scatter Gather Tables must be quadword aligned. Bits[2:0]
must be zeroes.
A PCI Target Abort occurred while the SiI3531A was fetching a Scatter Gather
Table from host memory.
A PCI Master Abort occurred while the SiI3531A was fetching a Scatter Gather
Table from host memory.
A PCI Parity Error occurred while the SiI3531A was fetching a Scatter Gather
Table from host memory.
The address of a PRB written to a command activation register was not aligned
on a quadword boundary. All PRB addresses must be quadword aligned.
Bits[2:0] must be zeroes.
A PCI Target Abort occurred while the SiI3531A was fetching a Port Request
Block (PRB) from host memory.
A PCI Master Abort occurred while the SiI3531A was fetching a Port Request
Block (PRB) from host memory.
A PCI Parity Error occurred while the SiI3531A was fetching a Port Request
Block (PRB) from host memory.
A PCI Target Abort occurred while data transfer was underway between the
SiI3531A and host memory.
A PCI Master Abort occurred while data transfer was underway between the
SiI3531A and host memory.
A PCI Parity Error occurred while data transfer was underway between the
SiI3531A and host memory.
A FIS was received while attempting to transmit a Service FIS. Following the
receipt of a Set Device Bits FIS containing a service request, the device sent
another FIS before allowing the host to send a Service FIS.
DEVICEERROR
1
SDBERROR
DATAFISERROR
2
3
SENDFISERROR
4
INCONSISTENTSTATE
5
DIRECTIONERROR
6
UNDERRUNERROR
7
OVERRUNERROR
8
PACKETPROTOCOLERROR
11
PLDSGTERRORBOUNDARY
16
PLDSGTERRORTARGETABORT
17
PLDSGTERRORMASTERABORT
18
PLDSGTERRORPCIPERR
19
PLDCMDERRORBOUNDARY
24
PLDCMDERRORTARGETABORT
25
PLDCMDERRORMASTERABORT
26
PLDCMDERRORPCIPERR
27
PSDERRORTARGETABORT
33
PSDERRORMASTERABORT
34
PSDERRORPCIPERR
35
SENDSERVICEERROR
36
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