參數(shù)資料
型號： SiI3531ACNU
廠商： Silicon Image, Inc.
英文描述： PCI Express to Serial ATA Controller
中文描述： PCI Express到串行ATA控制器
文件頁數(shù)： 11/81頁
文件大小： 553K
代理商： SII3531ACNU
PCI Express to Serial ATA Controller
Silicon Image, Inc.
2.2 SATA Interface Timing Specifications
Data Sheet
2006 Silicon Image, Inc.
SiI-DS-0208-C
11
Limits
Typ
Symbol
Parameter
Condition
Min
100
67
Max
273
136
Unit
T
TX_RISE_FALL
Rise and Fall time at
transmitter
Tx Frequency Long Term
Stability
20%-80% at Gen 1
20%-80% at Gen 2
ps
T
TX_TOL_FREQ
-350
+350
ppm
Table 2-5 SATA Interface Timing Specifications
2.3 SATA Interface Transmitter Output Jitter Characteristics
Limits
Typ
Symbol
Parameter
Condition
Min
Max
Unit
TJ
5UI_15G
Total Jitter, Data-Data 5UI
Measured at Tx output pins
peak to peak phase variation
Random data pattern
Measured at Tx output pins
peak to peak phase variation
Random data pattern
Measured at Tx output pins
peak to peak phase variation
Random data pattern
Measured at Tx output pins
peak to peak phase variation
Random data pattern
80
ps
DJ
5UI_15G
Deterministic Jitter, Data-
Data 5UI
50
ps
TJ
250UI_15G
Total Jitter, Data-Data
250UI
85
ps
DJ
250UI_15G
Deterministic Jitter, Data-
Data 250UI
55
ps
Table 2-6 SATA Interface Transmitter Output Jitter Characteristics, 1.5 Gb/s
Limits
Typ
Symbol
Parameter
Condition
Min
Max
Unit
TJ
fBAND/10_3G
Total Jitter, f
C3dB
=f
BAUD
/10
Measured at SATA Compliance
Point
clock pattern
Load = LL Laboratory Load
Measured at SATA Compliance
Point
clock pattern
Load = LL Laboratory Load
Measured at SATA Compliance
Point
Random data pattern
Load = LL Laboratory Load
Measured at SATA Compliance
Point
Random data pattern
Load = LL Laboratory Load
70*
ps
DJ
fBAND/10_3G
Deterministic Jitter,
f
C3dB
=f
BAUD
/10
45*
ps
TJ
fBAND/500_3G
Total Jitter, f
C3dB
=f
BAUD
/500
80
ps
DJ
fBAND/500_3G
Deterministic Jitter,
f
C3dB
=f
BAUD
/500
55
ps
Table 2-7 SATA Interface Transmitter Output Jitter Characteristics, 3 Gb/s
* With f
C3dB
=f
BAUD
/10 bandwidth, jitter analysis algorithm provided by oscilloscope manufacture requires full transition density
which is clock pattern. A series resistor of 75ohms should be populated close to the VDDX pin
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