參數(shù)資料
型號(hào)： SiI3531ACNU
廠商： Silicon Image, Inc.
英文描述： PCI Express to Serial ATA Controller
中文描述： PCI Express到串行ATA控制器
文件頁數(shù)： 4/81頁
文件大?。?/td> 553K
代理商： SII3531ACNU
PCI Express to Serial ATA Controller
Data Sheet
6.1
PCI Configuration Space........................................................................................................................ 43
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
6.1.8
6.1.9
6.1.10
6.1.11
6.1.12
6.1.13
6.1.14
6.1.15
6.1.16
6.1.17
6.1.18
6.1.19
6.1.20
6.1.21
6.1.22
6.1.23
6.1.24
6.1.25
6.1.26
6.1.27
6.1.28
6.1.29
6.1.30
6.1.31
6.1.32
6.1.33
6.2
Internal Register Space – Base Address 0........................................................................................... 56
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
6.2.10
6.3
Internal Register Space – Base Address 1........................................................................................... 61
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
6.3.10
6.3.11
6.3.12
6.3.13
6.3.14
6.3.15
6.3.16
6.3.17
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0208-C
4
Device ID – Vendor ID........................................................................................................................................44
PCI Status – PCI Command...............................................................................................................................44
PCI Class Code – Revision ID............................................................................................................................45
BIST – Header Type – Latency Timer – Cache Line Size..................................................................................45
Base Address Register 0....................................................................................................................................45
Base Address Register 1....................................................................................................................................46
Base Address Register 2....................................................................................................................................46
Subsystem ID – Subsystem Vendor ID ..............................................................................................................46
Capabilities Pointer.............................................................................................................................................47
Max Latency – Min Grant – Interrupt Pin – Interrupt Line...................................................................................47
Header Write Enable..........................................................................................................................................47
Power Management Capability...........................................................................................................................48
Power Management Control + Status.................................................................................................................48
MSI Capability ....................................................................................................................................................49
Message Address...............................................................................................................................................49
MSI Message Data.............................................................................................................................................49
PCI Express Capability.......................................................................................................................................50
Device Capabilities.............................................................................................................................................50
Device Status and Control..................................................................................................................................51
Link Capabilities .................................................................................................................................................51
Link Status and Control......................................................................................................................................52
Global Register Offset........................................................................................................................................52
Global Register Data..........................................................................................................................................52
Port Register Offset............................................................................................................................................53
Port Register Data..............................................................................................................................................53
Advanced Error Reporting Capability .................................................................................................................53
Uncorrectable Error Status.................................................................................................................................54
Uncorrectable Error Mask...................................................................................................................................54
Uncorrectable Error Severity ..............................................................................................................................54
Correctable Error Status.....................................................................................................................................55
Correctable Error Mask ......................................................................................................................................55
Advanced Error Capabilities and Control............................................................................................................55
Header Log.........................................................................................................................................................56
Port Slot Status Register....................................................................................................................................57
Global Control ....................................................................................................................................................57
Global Interrupt Status........................................................................................................................................58
PHY Configuration..............................................................................................................................................58
BIST Control Register.........................................................................................................................................58
BIST Pattern Register.........................................................................................................................................59
BIST Status Register..........................................................................................................................................59
MemBIST Status Register..................................................................................................................................59
Configuration Register Offset .............................................................................................................................59
Configuration Register Data...............................................................................................................................60
Port LRAM..........................................................................................................................................................62
Port Slot Status ..................................................................................................................................................63
Port Control Set..................................................................................................................................................63
Port Status..........................................................................................................................................................64
Port Control Clear...............................................................................................................................................65
Port Interrupt Status ...........................................................................................................................................65
Port Interrupt Enable Set / Port Interrupt Enable Clear.......................................................................................66
32-bit Activation Upper Address.........................................................................................................................66
Port Command Execution FIFO .........................................................................................................................67
Port Command Error ..........................................................................................................................................67
Port FIS Configuration........................................................................................................................................69
Port PCI Express Request FIFO Threshold........................................................................................................70
Port 8B/10B Decode Error Counter....................................................................................................................70
Port CRC Error Counter .....................................................................................................................................71
Port Handshake Error Counter...........................................................................................................................71
Port PHY Configuration......................................................................................................................................71
Port Device Status Register ...............................................................................................................................73
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