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參數(shù)資料
| 型號： | SII3531A |
| 廠商： | Silicon Image, Inc. |
| 英文描述： | PCI Express to Serial ATA Controller |
| 中文描述： | PCI Express到串行ATA控制器 |
| 文件頁數(shù)： | 65/81頁 |
| 文件大?。?/td> | 553K |
| 代理商： | SII3531A |
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PCI Express to Serial ATA Controller
Silicon Image, Inc.
6.3.5 Port Control Clear
Address Offset: 1004
H
Access Type: Write One To Clear
Reset Value: N/A
Data Sheet
2006 Silicon Image, Inc.
SiI-DS-0208-C
65
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
O
Reserved
L
A
P
R
3
S
C
T
R
P
L
I
R
P
This register is used to direct various port operations. A one written to a bit position clears that bit in the control register.
Bit [31:26,24:16,12:11,2:1]
: Reserved (R). These bits are reserved.
Bit [25,15:13,10:3,0]
: (W1C) Writing a one to these bits clears the associated bit position of the Port Control
register. Refer to the Port Control Set register for bit descriptions.
6.3.6 Port Interrupt Status
Address Offset: 1008
H
Access Type: Read/Write 1 Clear
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
S
H
C
8
D
U
C
P
P
P
C
C
Reserved
S
H
C
8
D
U
C
P
P
P
C
C
This register is used to report the interrupt status. The status bits in the upper half of the register report the described
condition. The status bits in the lower half of the register are masked by the corresponding interrupt enable bits or by the
setting in the corresponding threshold registers. Writing a 1 to either interrupt status bit clears it.
Bit [31:28,15:12]
: Reserved (R). These bits are reserved.
Bit [27/11]
: SDB Notify (W1C). This bit indicates that a Set Device Bits FIS was received with the N-bit (bit 15
of first dword) set to one.
Bit [26/10]
: Handshake Error Threshold (W1C). This bit indicates that the Handshake error count is equal to or
greater than the Handshake error threshold. Bit 10 is masked if the Handshake Error Threshold register contains
a zero threshold setting. When a 1 is written to this bit, both the status bit and the Handshake Error Counter are
cleared.
Bit [25/9]
: CRC Error Threshold (W1C). This bit indicates that the CRC error count is equal to or greater than
the CRC error threshold. Bit 9 is masked if the CRC Error Threshold register contains a zero threshold setting.
When a 1 is written to this bit, both the status bit and the CRC Error Counter are cleared.
Bit [24/8]
: 8b/10b Decode Error Threshold (W1C). This bit indicates that the 8b/10b Decode error count is
equal to or greater than the 8b/10b Decode error threshold. Bit 8 is masked if the 8b/10b Decode Error
Threshold register contains a zero threshold setting. When a 1 is written to this bit, both the status bit and the
8b/10b Decode Error Counter are cleared.
Bit [23/7]
: DevExchg (Device Exchanged) (W1C) – This bit is the X bit in the DIAG field of the SError register. It
may be cleared by writing a corresponding one bit to either register.
Bit [22/6]
: UnrecFIS (Unrecognized FIS Type) (W1C) – This bit is the F bit in the DIAG field of the SError
register. It may be cleared by writing a corresponding one bit to either register.
Bit [21/5]
: ComWake (W1C) – This bit is the W bit in the DIAG field of the SError register. It may be cleared by
writing a corresponding one bit to either register.
Bit [20/4]
: PhyRdyChg (W1C) – This bit is the N bit in the DIAG field of the SError register. It may be cleared by
writing a corresponding one bit to either register.
Bit [19/3]
: PM Change (W1C). This bit indicates that a change has occurred in the power management state.
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| SiI3723CNU | 制造商:Silicon Image Inc 功能描述: |
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