
PCI Express to Serial ATA Controller
Silicon Image, Inc.
Data Sheet
2006 Silicon Image, Inc.
SiI-DS-0208-C
43
6 Register Definitions
This section describes the registers within the SiI3531A.
6.1 PCI Configuration Space
The PCI Configuration Space registers define the operation of the SiI3531A on the PCI Express bus.
Address
Offset
00
H
04
H
08
H
0C
H
10
H
14
H
18
H
1C
H
20
H
24
H
28
H
2C
H
30
H
34
H
38
H
3C
H
40
H
44
H
48
H
4C
H
50
H
54
H
58
H
5C
H
60
H
64
H
68
H
6C
H
70
H
74
H
78
H
7C
H
80
H
84
H
-EF
H
F0
H
-FF
H
100
H
104
H
108
H
10C
H
110
H
114
H
118
H
11C
H
-12B
H
Register Name
Device ID
PCI Status
Vendor ID
PCI Command
PCI Class Code
Header Type
Revision ID
Cache Line Size
BIST
Latency Timer
Base Address Register 0
Base Address Register 1
Base Address Register 2
Reserved
Reserved
Subsystem ID
Subsystem Vendor ID
Reserved
Reserved
Capabilities Ptr
Reserved
Max Latency
Min Grant
Interrupt Pin
Interrupt Line
Reserved
Reserved
Reserved
Hdr Wr Ena
Reserved
Reserved
Power Management Capabilities
Data
Message Control
Next Capability
Pwr Mgt Cap ID
Reserved
Control and Status
Next Capability
MSI Cap ID
Message Address
Reserved
Message Data
Reserved
PCI Express Capabilities Register
Next Capability
PCI Exp Cap ID
Device Capabilities
Device Status
Device Control
Link Capabilities
Link Status
Link Control
Reserved
Indirect Access
Advanced Error Reporting Capability
Uncorrectable Error Status
Uncorrectable Error Mask
Uncorrectable Error Severity
Correctable Error Status
Correctable Error Mask
Advanced Error Capabilities and Control
Header Log
Table 6-1 SiI3531A PCI Configuration Space