參數(shù)資料
型號： SII3531A
廠商： Silicon Image, Inc.
英文描述： PCI Express to Serial ATA Controller
中文描述： PCI Express到串行ATA控制器
文件頁數(shù)： 54/81頁
文件大小： 553K
代理商： SII3531A
PCI Express to Serial ATA Controller
Data Sheet
6.1.27 Uncorrectable Error Status
Address Offset: 104
H
Access Type: Read/Write 1 to Clear
Reset Value: 0x0000_0000
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0208-C
54
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
U
E
M
R
U
C
C
F
P
Reserved
S
D
Reserved
U
Bit [31:21,11:06,03:01]
: Reserved (R) – These bits are reserved and return zero on a read.
Bit [20]
: Unsup Req Err (R/W1C) – Unsupported Request Error Status.
Bit [19]
: ECRC Error (R/W1C) – ECRC Error Status.
Bit [18]
: Malformed TLP (R/W1C) – Malformed TLP Status.
Bit [17]
: Rx Overflow (R) – Receiver Overflow Status; always 0.
Bit [16]
: Unexp Comp (R/W1C) – Unexpected Completion Status.
Bit [15]
: Comp Abort (R/W1C) – Completer Abort Status.
Bit [14]
: Comp Timeout (R/W1C) – Completion Timeout Status.
Bit [13]
: FC Protocol Err (R/W1C) – Flow Control Protocol Error Status. This bit is hardwired to 0 (as are its
mask and error severity bits).
Bit [12]
: Poisoned TLP (R/W1C) – Poisoned TLP Status.
Bit [05]
: Surprise Down (R/W1C) – Surprise Down Error Status.
Bit [04]
: DL Protocol Err (R/W1C) – Data Link Protocol Error Status.
Bit [00]
: Undefined (R/W) – This bit is reset to 0, but may be written. The definition of this bit was changed in
revision 1.1 of the PCI-Express specification.
6.1.28 Uncorrectable Error Mask
Address Offset: 108
H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
U
E
M
R
U
C
C
F
P
Reserved
S
D
Reserved
U
The bits of this register are the mask bits for corresponding bits of the Uncorrectable Error Status register.
6.1.29 Uncorrectable Error Severity
Address Offset: 10C
H
Access Type: Read/Write
Reset Value: 0x0006_2031
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
U
E
M
R
U
C
C
F
P
Reserved
S
D
Reserved
U
The bits of this register are the error severity bits for corresponding bits of the Uncorrectable Error Status register.
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