
PCI Express to Serial ATA Controller
Silicon Image, Inc.
6.1.30 Correctable Error Status
Address Offset: 110
H
Access Type: Read/Write 1 to Clear
Reset Value: 0x0000_0000
Data Sheet
2006 Silicon Image, Inc.
SiI-DS-0208-C
55
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
A
F
R
Reserved
R
B
B
Reserved
R
Bit [31:14,11:09,05:01]
: Reserved (R) – These bits are reserved and return zero on a read.
Bit [13]
: Advis Non-Fatal (R/W1C) – Advisory Non-Fatal Error Status.
Bit [12]
: Replay Timeout (R/W1C) – Replay Timer Timeout Status.
Bit [08]
: REPLAY_NUM (R/W1C) – REPLAY_NUM Rollover Status.
Bit [07]
: Bad DLLP (R/W1C) – Bad DLLP Status.
Bit [06]
: Bad TLP (R/W1C) – Bad TLP Status.
Bit [00]
: Rx Error (R/W1C) – Receiver Error Status. This bit is hardwired to 0 (as is the corresponding mask
bit).
6.1.31 Correctable Error Mask
Address Offset: 114
H
Access Type: Read/Write
Reset Value: 0x0000_2000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
A
F
R
Reserved
R
B
B
Reserved
R
The bits of this register are the mask bits for corresponding bits of the Correctable Error Status register.
6.1.32 Advanced Error Capabilities and Control
Address Offset: 118
H
Access Type: Read/Write
Reset Value: 0x0000_00A0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
E
E
E
E
First Error Pointer
Bit [31: 09]
: Reserved (R) – These bits are reserved and return zero on a read.
Bit [08]
: ECRC Chk En (R/W) – ECRC Check Enable.
Bit [07]
: ECRC Chk Cap (R) – ECRC Check Capable. This bit is hardwired to 1.
Bit [06]
: ECRC Gen En (R/W) – ECRC Generation Enable.
Bit [05]
: ECRC Gen Cap (R) – ECRC Generation Capable. This bit is hardwired to 1.
Bit [04:00]
: First Error Pointer (R).