參數(shù)資料
型號： SII3531A
廠商： Silicon Image, Inc.
英文描述： PCI Express to Serial ATA Controller
中文描述： PCI Express到串行ATA控制器
文件頁數(shù)： 52/81頁
文件大?。?/td> 553K
代理商： SII3531A
PCI Express to Serial ATA Controller
Data Sheet
6.1.21 Link Status and Control
Address Offset: 80
H
Access Type: Read/Write
Reset Value: 0x0011_0000 or 0x1011_0000
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0208-C
52
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
S
L
L
Negotiated Link Width
Link Speed
Reserved
E
C
R
L
R
R
A
Bit [31:29,15:08,02]
: Reserved (R) – These bits are reserved and return zero on a read.
Bit [28]
: Slot Clk Config (R) – Slot Clock Configuration. This bit is 1 if the reference clock is detected.
Bit [27]
: Link Training (R) –This bit is hardwired to 0.
Bit [26]
: Link Train Err (R) – This bit is hardwired to 0.
Bit [25:20]
: Negotiated Link Width (R) – This bit field is hardwired to 000001
B
.
Bit [19:16]
: Link Speed (R) – This bit field is hardwired to 0001
B
.
Bit [07]
: Ext Synch (R/W) – Extended Synch.
Bit [06]
: Comm Clk Cfg (R/W) – Common Clock Configuration.
Bit [05]
: Retrain Link (R) – This bit is hardwired to 0.
Bit [04]
: Link Disable (R) – This bit is hardwired to 0.
Bit [03]
: RCB (R/W) – Read Completion Boundary.
Bit [01:00]
: ASPM Control (R/W)
6.1.22 Global Register Offset
Address Offset: F0
H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Dword Offset
00
This register provides indirect addressing of a Global Register otherwise accessible directly via Base Address Register 0. The
Dword address offset for an indirect access is in bits 6 to 2; bits 31 to 7, 1, and 0 are reserved and should always be 0.
Note that this is physically the same register as that addressed by Base Address Register 2, Offset 00
H
.
6.1.23 Global Register Data
Address Offset: F4
H
Access Type: Read/Write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
As defined for indirectly accessed register
This register provides the indirect access addressed by the Global Register Offset register.
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