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參數(shù)資料
| 型號： | SII3531A |
| 廠商： | Silicon Image, Inc. |
| 英文描述： | PCI Express to Serial ATA Controller |
| 中文描述： | PCI Express到串行ATA控制器 |
| 文件頁數(shù)： | 44/81頁 |
| 文件大?。?/td> | 553K |
| 代理商： | SII3531A |
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PCI Express to Serial ATA Controller
Data Sheet
6.1.1 Device ID – Vendor ID
Address Offset: 00
H
Access Type: Read /Write
Reset Value: 0x3531_1095
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0208-C
44
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Device ID
Vendor ID
This register defines the Device ID and Vendor ID associated with the SiI3531A. The register bits are defined below.
Bit [31:16]
: Device ID (R/W) – Device ID. The value in this bit field is one of the following:
the default value of 0x3531 to identify the device as a Silicon Image SiI3531A.
system programmed value; if bit 0 of the Configuration register (48
H
) is set, the Device ID is system
programmable.
Bit [15:00]
: Vendor ID (R) – Vendor ID. This field defaults to 0x1095 to identify the vendor as Silicon Image.
6.1.2 PCI Status – PCI Command
Address Offset: 04
H
Access Type: Read/Write/Write-One-to-Clear
Reset Value: 0x0010_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
C
D
S
R
R
S
R
D
R
I
Reserved
I
R
S
R
P
R
B
M
I
This register defines the various control functions associated with the PCI bus. The register bits are defined below.
Bit 31
: Det Par Err (R/W1C) – Detected Parity Error.
Bit 30
: Sig Sys Err (R/W1C) – Signaled System Error.
Bit 29
: Rcvd M Abort (R/W1C) – Received Master Abort.
Bit 28
: Rcvd T Abort (R/W1C) – Received Target Abort.
Bit 27
: Sig T Abort (R/W1C) – Signaled Target Abort.
Bit 24
: Det M Par Err (R/W1C) – Detected Master Data Parity Error.
Bit 20
: Capabilities List (R) – PCI Capabilities List. This bit is hardwired to 1 to indicate that the SiI3531A
implements Capabilities registers for Power Management, PCI-X, and Message Signaled Interrupt.
Bit [19]
: Interrupt Status (R).
Bit [26:25,23:21,18:11,9,7,5:3]
: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [10]
: Interrupt Disable (R/W).
Bit 08
: SERR Enable (R/W) – SERR Enable.
Bit 06
: Par Error Resp (R/W) – Parity Error Response Enable.
Bit 02
: Bus Master (R/W) – Bus Master Enable. This bit set enables the SiI3531A to act as PCI bus master, i.e.,
issue Memory Requests.
Bit 01
: Memory Space (R/W) – Memory Space Enable. This bit set enables the SiI3531A to respond to memory
space accesses.
Bit 00
: I/O Space (R/W) – I/O Space Enable. This bit set enables the SiI3531A to respond to I/O space
accesses.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SiI3531ACNU | PCI Express to Serial ATA Controller |
| SII3531 | SteelVine⑩ Host Controller |
| SII3611 | SATALink Device Bridge |
| SII3726 | SATA Port Multiplier |
| SiI3726CB | SATA Port Multiplier |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SII3531ACNU | 制造商:Silicon Image Inc 功能描述:PCI Express to Serial ATA Controller 48-Pin QFN EP |
| SII3611 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:SATALink Device Bridge |
| SII3611CT80-1.5 | 制造商:SILICON IMAGE 功能描述:3611CT80-1.5 |
| SII3723 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:Third Generation SATA Port Multiplier Storage Processor |
| SiI3723CNU | 制造商:Silicon Image Inc 功能描述: |
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