參數(shù)資料
型號: SI3230PPQX-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 99/108頁
文件大?。?/td> 0K
描述: BOARD EVAL W/DISCRETE INTERFACE
標準包裝: 1
系列: ProSLIC®
主要目的: 接口,模擬前端(AFE)
已用 IC / 零件: Si3230
已供物品: 板,CD
Si3230
90
Preliminary Rev. 0.96
Not
Recommended
fo
r N
ew
D
esi
gn
s
Reset settings = 0000_1000
Reset settings = 0000_0000
Register 107. DC Peak Current Monitor Calibration Result
Bit
D7D6D5D4D3D2
D1
D0
Name
CMDCPK[3:0]
Type
R/W
Bit
Name
Function
7:4
Reserved
Read returns zero.
3:0
CMDCPK[3:0]
DC Peak Current Monitor Calibration Result.
Register 108. Enhancement Enable
Bit
D7D6D5D4D3D2
D1
D0
Name
ILIMEN
FSKEN
DCSU
ZSEXT
LCVE
DCFIL
HYSTEN
Type
R/W
Bit
Name
Function
7ILIMEN
Current Limit Increase.
When enabled, this bit temporarily increases the maximum differential current limit at the
end of a ring burst to enable a faster settling time to a dc linefeed state.
0 = The value programmed in ILIM (direct Register 71) is used.
1 = The maximum differential loop current limit is temporarily increased to 41 mA.
6
FSKEN
FSK Generation Enhancement.
When enabled, this bit will increase the clocking rate of tone generator 1 to 24 kHz only
when the REL bit (direct Register 32, bit 6) is set. Also, dedicated oscillator registers are
used for FSK generation (indirect registers 99–104). Audio tones are generated using
this new higher frequency, and oscillator 1 active and inactive timers have a finer bit res-
olution of 41.67
s. This provides greater resolution during FSK caller ID signal genera-
tion.
0 = Tone generator always clocked at 8 kHz; OSC1, OSC1X., and OSC1Y are always
used.
1 = Tone generator module clocked at 24 kHz and dedicated FSK registers used only
when REL = 1; otherwise clocked at 8 kHz.
5
DCSU
DC-DC Converter Control Speedup.
When enabled, this bit invokes a multi-threshold error control algorithm which allows the
dc-dc converter to adjust more quickly to voltage changes.
0 = Normal control algorithm used.
1 = Multi-threshold error control algorithm used.
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