參數(shù)資料
型號(hào)： SI3230PPQX-EVB
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 28/108頁(yè)
文件大小： 0K
描述： BOARD EVAL W/DISCRETE INTERFACE
標(biāo)準(zhǔn)包裝： 1
系列： ProSLIC®
主要目的： 接口，模擬前端（AFE）
已用 IC / 零件： Si3230
已供物品： 板，CD
Si3230
26
Preliminary Rev. 0.96
Not
Recommended
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2.2.5. DC-DC Converter Enhancements
There are two enhancements to the dc-dc converter.
The first is a multi-threshold error control algorithm that
enables the dc-dc converter to adjust more quickly to
voltage changes. This option is enabled by setting
DCSU = 1 (direct Register 108, bit 5). The second
enhancement is an audio band filter that removes audio
band noise from the dc-dc converter control loop. This
option
is
enabled
by
setting
DCFIL = 1
(direct
Register 108, bit 1).
2.2.6. DC-DC Converter During Ringing
When the ProSLIC enters the ringing state, it requires
voltages well above those used in the active mode. The
voltage to be generated and regulated by the dc-dc
converter during a ringing burst is set using the VBATH
register (direct Register 74). VBATH can be set between
0 and –94.5 V in 1.5 V steps. To avoid clipping the
ringing signal, VBATH must be set larger than the ringing
amplitude. At the end of each ringing burst the dc-dc
converter adjusts back to active state regulation as
described above.
2.3. Tone Generation
Two digital tone generators are provided in the ProSLIC.
They allow the generation of a wide variety of single or
dual tone frequency and amplitude combinations and
spare the user the effort of generating the required
POTS signaling tones on the PCM highway. DTMF, FSK
(caller ID), call progress, and other tones can all be
generated on-chip.
2.3.1. Tone Generator Architecture
A simplified diagram of the tone generator architecture
is shown in Figure 11. The oscillator, active/inactive
timers, interrupt block, and signal routing block are
connected to give the user flexibility in creating audio
signals. Control and status register bits are placed in the
figure to indicate their association with the tone
generator architecture. These registers are described in
more detail in Table 25.
Figure 11. Simplified Tone Generator Diagram
OZn
OSSn
*Tone Generator 1 Only
n = "1" or "2" for Tone Generator 1 and 2, respectively
Two-Pole
Resonance
Oscillator
16-Bit
Modulo
Counter
OATn
OITn
OITnE
OATnE
OSCn
OSCnY
OSCnX
Load
Logic
Zero
Cross
Logic
Signal
Routing
OnSO
to TX Path
to RX Path
INT
Logic
OnIP
OnIE
INT
Logic
OnAP
OnAE
REL*
Register
Load
Enable
8 kHz
Clock
Zero Cross
OnE
OAT
Expire
OIT
Expire
8 kHz
Clock
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