參數(shù)資料
型號: SI3230PPQX-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 65/108頁
文件大?。?/td> 0K
描述: BOARD EVAL W/DISCRETE INTERFACE
標準包裝: 1
系列: ProSLIC®
主要目的: 接口,模擬前端(AFE)
已用 IC / 零件: Si3230
已供物品: 板,CD
Si3230
6
Preliminary Rev. 0.96
Not
Recommended
fo
r N
ew
D
esi
gn
s
Longitudinal Performance
Longitudinal to Metallic Balance
200 Hz to 3.4 kHz,
Q1,Q2
150, 1% mismatch
56
60
dB
Q1,Q2 60 to 240
43
60
dB
Q1,Q2 300 to 800
53
60
dB
Using Si3201
TBD
60
dB
Metallic to Longitudinal Balance
200 Hz to 3.4 kHz
40
dB
Longitudinal Impedance
200 Hz to 3.4 kHz at TIP or
RING
Register selectable
ETBO/ETBA
00
01
10
33
17
Longitudinal Current per Pin
Active off-hook
200 Hz to 3.4 kHz
Register selectable
ETBO/ETBA
00
01
10
4
8
mA
Table 3. AC Characteristics (Continued)
(VDDA, VDDD = 3.13 to 5.25 V, TA = 0 to 70°C for K-Grade, –40 to 85°C for B-Grade)
Parameter
Test Condition
Min
Typ
Max
Unit
Notes:
1. Analog signal measured as VTIP – VRING. Assumes ideal line impedance matching.
2. The quantization errors inherent in the
/A-law companding process can generate slightly worse gain tracking
performance in the signal range of 3 dB to –37 dB for signal frequencies that are integer divisors of the 8 kHz PCM
sampling rate.
3. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm.
4. Assumes normal distribution of betas.
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