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參數(shù)資料
| 型號： | SI3230PPQX-EVB |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 26/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL W/DISCRETE INTERFACE |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ProSLIC® |
| 主要目的： | 接口，模擬前端（AFE） |
| 已用 IC / 零件： | Si3230 |
| 已供物品： | 板，CD |
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Si3230
24
Preliminary Rev. 0.96
Not
Recommended
fo
r N
ew
D
esi
gn
s
voltage to the dc-dc converter external circuitry. If an
overload condition is detected, the PWM controller will
turn off the switching transistor for the remainder of a
PWM
period
to
prevent
damage
to
external
components. It is important that the proper value of R18
be selected to ensure safe operation. Guidance is given
in Application Note 45 (AN45).
The PWM controller operates at a frequency set by the
dc-dc Converter PWM register (direct Register 92).
During a PWM period the outputs of the control pins
DCDRV and DCFF are asserted for a time given by the
read-only
PWM
Pulse
Width
register
(direct
Register 94).
The dc-dc converter must be off for some time in each
cycle to allow the inductor or transformer to transfer its
stored energy to the output capacitor, C9. This minimum
off time can be set through the dc-dc Converter
Switching Delay register, (direct Register 93). The
number of 16.384 MHz clock cycles that the controller is
off is equal to DCTOF (bits 0 through 4) plus 4. If the dc
Monitor pins detect an overload condition, the dc-dc
converter interrupts its conversion cycles regardless of
the register settings to prevent component damage.
These inputs should be calibrated by writing the DCCAL
bit (bit 7) of the dc-dc Converter Switching Delay
register, direct Register 93, after the dc-dc converter
has been turned on.
Because the Si3230 dynamically regulates its own
battery supply voltage using the dc-dc converter
controller, the battery voltage (VBAT) is offset from the
negative-most terminal by a programmable voltage
(VOV) to allow voltage headroom for carrying audio
signals.
As mentioned previously, the Si3230 dynamically
adjusts VBAT to suit the particular circuit requirement. To
illustrate this, the behavior of VBAT in the active state is
shown in Figure 10. In the active state, the TIP-to-RING
open circuit voltage is kept at VOC in the constant
voltage region while the regulator output voltage, VBAT =
VCM + VOC + VOV.
When the loop current attempts to exceed ILIM, the dc
line driver circuit enters constant current mode allowing
the TIP to RING voltage to track RLOOP. As the TIP
terminal is kept at a constant voltage, it is the RING
terminal voltage that tracks RLOOP and, as a result, the
|VBAT| voltage will also track RLOOP. In this state, |VBAT|
= ILIM x RLOOP + VCM +VOV. As RLOOP decreases below
the VOC/ILIM mark, the regulator output voltage can
continue to track RLOOP (TRACK = 1), or the RLOOP
tracking mechanism is stopped when |VBAT| = |VBATL|
(TRACK = 0). The former case is the more common
application
and
provides
the
maximum
power
dissipation savings. In principle, the regulator output
voltage can go as low as |VBAT|=VCM+ VOV, offering
significant power savings.
When TRACK = 0, |VBAT| will not decrease below
VBATL. The RING terminal voltage, however, continues
to
decrease with
decreasing
RLOOP. The power
dissipation on the NPN bipolar transistor driving the
RING terminal can become large and may require a
higher power rating device. The non-tracking mode of
operation is required by specific terminal equipment
which, in order to initiate certain data transmission
modes, goes briefly on-hook to measure the line voltage
to determine whether there is any other off-hook
terminal equipment on the same line. TRACK = 0 mode
is desired since the regulator output voltage has long
settling time constants (on the order of tens of
milliseconds) and cannot change rapidly for TRACK = 1
mode.
Therefore,
the
brief
on-hook
voltage
measurement would yield approximately the same
voltage as the off-hook line voltage and would cause the
terminal equipment to incorrectly sense another off-
hook terminal.
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