參數資料
型號： SI3225PPT0-EVB
廠商： Silicon Laboratories Inc
文件頁數： 99/112頁
文件大?。?/td> 0K
描述： BOARD EVAL W/SI3200 INTERFACE
標準包裝： 1
系列： ProSLIC®
類型： ADC + DAC，編碼解碼器，前端
適用于相關產品： Si3225
所含物品： 評估板和光盤
Si3220/25 Si3200/02
Rev. 1.3
87
Not
Recommended
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ew
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The Idle state is achieved by the MX and MR bits being
held inactive for two or more frames. When a
transmission is initiated by a host device, an active state
is seen on the downstream MX bit. This signals the Dual
ProSLIC that a transmission has begun on the Monitor
channel and it should begin accepting data from it. After
reading the data on the monitor channel, the Dual
ProSLIC acknowledges the initial transmission by
placing the upstream MR bit in an active state. The data
is received, and the upstream MR becomes active in the
frame immediately following the downstream MX
activation. The upstream MR then remains active until
either the next byte is received or an end of message is
detected (signaled by the downstream MX being held
inactive for two or more consecutive frames). Upon
receiving acknowledgement from the Dual ProSLIC that
the initial data was received (signaled by the upstream
MR bit transitioning from an active to an inactive state),
the host device places the downstream MX bit in the
inactive state for one frame and then either transmits
another byte by placing the downstream MX bit in an
active state again or signals an end of message by
leaving the downstream MX bit inactive for a second
frame.
When the host is performing a write command, the host
only manipulates the downstream MX bit, and the Dual
ProSLIC only manipulates the upstream MR bit. If a
read
command
is
performed,
the
host
initially
manipulates the downstream MX bit to communicate
the command but then manipulates the downstream MR
bit in response to the Dual ProSLIC responding with the
requested data. Similarly, the Dual ProSLIC initially
manipulates its upstream MR bit to receive the read
command and then manipulates its upstream MX bit to
respond with the requested data. If the host is
transmitting data, the Dual ProSLIC always transmits a
$FF value on its Monitor data byte. While the Dual
ProSLIC is transmitting data, the host should always
transmit a $FF value on its Monitor byte. If the Dual
ProSLIC is transmitting data and detects a value other
than a $FF on the downstream Monitor byte, the Dual
ProSLIC signals an abort.
For read and write commands, an initial address must
be specified. The Dual ProSLIC responds to a read or a
write command at this address and then subsequently
increments this address after every register access. In
this manner, multiple consecutive registers can be read
or written in one transmission sequence.
By correctly manipulating the MX and MR bits, a
transmission sequence can continue from the beginning
specified address until an invalid memory location is
reached. To end a transmission sequence, the host
processor must signal an End-of-Message (EOM) by
placing the downstream MX and MR bits inactive for two
consecutive frames. The transmission can also be
stopped by the Dual ProSLIC by signaling an abort. This
is signaled by placing the upstream MR bit inactive for
at least two consecutive cycles in response to the
downstream MX bit going active. An abort is signaled by
the Dual ProSLIC for the following reasons:
A read or write to an invalid memory address is
attempted.
An invalid command sequence is received.
A data byte was not received for at least two
consecutive frames.
A collision occurs on the Monitor data bytes while
the Dual ProSLIC is transmitting data.
Downstream monitor byte not $FF while upstream
monitor byte is transmitting.
MR/MX protocol violation.
Whenever the Dual ProSLIC aborts due to an invalid
command sequence, the state of the Dual ProSLIC
does not change. If a read or write to an invalid memory
address is attempted, all previous reads or writes in that
transmission sequence are valid up to the read or write
to the invalid memory address. If an end-of-message is
detected
before
a
valid
command
sequence
is
communicated, the Dual ProSLIC returns to the idle
state and remains unchanged.
The data presented to the Dual ProSLIC in the
downstream Monitor bits must be present for two
consecutive frames to be considered valid data. The
Dual ProSLIC is designed to ensure it has received the
same data in two consecutive frames. If it does not, it
does not acknowledge receipt of the data byte and waits
until it does receive two consecutive identical data bytes
before acknowledging to the transmitter that it has
received the data. If the transmitter attempts to signal
transmission of a subsequent data byte by placing the
downstream MX bit in an inactive state while the Dual
ProSLIC is still waiting to receive a valid data byte
transmission of two consecutive identical data bytes,
the Dual ProSLIC signals an abort and ends the
transmission. Figure 58 shows a state diagram for the
Receiver Monitor channel for the Dual ProSLIC.
Figure 59 shows a state diagram for the Transmitter
Monitor channel for the Dual ProSLIC.
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相關代理商/技術參數
參數描述
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