參數(shù)資料
型號： SI3225PPT0-EVB
廠商： Silicon Laboratories Inc
文件頁數(shù)： 53/112頁
文件大?。?/td> 0K
描述： BOARD EVAL W/SI3200 INTERFACE
標準包裝： 1
系列： ProSLIC®
類型： ADC + DAC，編碼解碼器，前端
適用于相關(guān)產(chǎn)品： Si3225
所含物品： 評估板和光盤
Si3220/25 Si3200/02
Rev. 1.3
45
Not
Recommended
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3.10. Loop Closure Detection
Loop closure detection is required to accurately signal a
terminal device going off-hook during the Active, On-
Hook Transmission (forward or reverse polarity), and
ringing linefeed states. The functional blocks required to
implement a loop closure detector are shown in
Figure 21, and the register set for detecting a loop
closure event is provided in Table 25. The primary input
to the system is the loop current sense value from the
voltage/current/power
monitoring
circuitry
and
is
reported in the ILOOP RAM address.
The loop current (ILOOP) is computed by the input signal
processor (ISP) using the equations shown below.
Refer to Figure 18 on page 38 for the discrete bipolar
transistor references) used in the equation below (Q1,
Q2, Q5 and Q6 – note that the Si3200/2 has
corresponding MOS transistors). The same ILOOP
equation applies to the discrete bipolar linefeed as well
as the Si3200/2 linefeed device. The following equation
is conditioned by the CMH status bit in register LCRRTP
and by the linefeed state as indicated by the LFS field in
the LINEFEED register.
If the CMHITH (RAM 36) threshold is exceeded, the
CMH bit is 1, and IQ1 is forced to zero in the
FORWARD-ACTIVE and TIP-OPEN states, or IQ2 is
forced to zero in the REVERSE-ACTIVE and RING-
OPEN states. The other currents in the equation are
allowed to contribute normally to the ILOOP value.
The conditioning due to the CMH bit (LCRRTP Register)
and LFS field (LINEFEED Register) states can be
summarized as follows:
IQ1 = 0 if (CMH = 1 AND (LFS = 1 OR LFS = 3))
IQ2 = 0 if (CMH = 1 AND (LFS = 5 OR LFS = 7))
The output of the ISP is the input to a programmable
digital low-pass filter that removes unwanted ac signal
components before threshold detection.
The low-pass filter coefficient is calculated using the
following equation and is entered into the LCRLPF RAM
location:
LCRLPF = [(2
f x 4096)/800] x 23
Where f = the desired cutoff frequency of the filter.
The programmable range of the filter is from 0h (blocks
all signals) to 4000h (unfiltered). A typical value of 10
(0A10h) is sufficient to filter out any unwanted ac
artifacts while allowing the dc information to pass
through the filter.
The output of the low-pass filter is compared to a
programmable threshold, LCROFFHK. Hysteresis is
enabled
by
programming
a
second
threshold,
LCRONHK, to detect the loop going to an open or on-
hook state. The threshold comparator output feeds a
programmable debounce filter. The output of the
debounce filter remains in its present state unless the
input remains in the opposite state for the entire period
of time programmed by the loop closure debounce
interval, LCRDBI. There is also a loop closure mask
interval, LCRMASK, that is used to mask transients
caused when an internal ringing burst (with no offset)
ends in the presence of a high REN load. If the
debounce interval has been satisfied, the LCR bit is set
to indicate that a valid loop closure has occurred.
Figure 21. Loop Closure Detection Circuitry
I
loop
I
Q1
I
Q6
–
I
Q5
I
Q2 in TIP-OPEN or RING-OPEN
I
Q1
I
Q6
–
I
Q5
I
Q2
–
+
2
---------------------------------------------------- in all other states
=
–
+
=
I
Q1
LFS
LCRLPF
LCROFFHK
Input
Signal
Processor
Digital
LPF
Loop Closure
Threshold
Debounce
Filter
+
–
LCR
LCRONHK
LOOPS
LOOPE
Interrupt
Logic
LCRDBI
Loop
Closure
Mask
LCRMASK
I
Q2
I
Q5
I
Q6
CMH
I
LOOP
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