參數(shù)資料
型號(hào): SI3225PPT0-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 6/112頁
文件大?。?/td> 0K
描述: BOARD EVAL W/SI3200 INTERFACE
標(biāo)準(zhǔn)包裝: 1
系列: ProSLIC®
類型: ADC + DAC,編碼解碼器,前端
適用于相關(guān)產(chǎn)品: Si3225
所含物品: 評(píng)估板和光盤
Si3220/25 Si3200/02
Rev. 1.3
103
Not
Recommended
fo
r N
ew
D
esi
gn
s
28, 52,
53
NC
No Internal Connection.
Leave unconnected or connect to ground plane.
28, 52
RTRPb,
RTRPa
I
External Ring Trip Sensing Input.
Used to sense ring-trip condition when using centralized ring
generator. Connect to low side of ring sense resistor.
30, 50
TRD2b,
TRD2a
O
Test Relay Driver Output.
Drives test relays for connecting loop test equipment.
31, 48
RRDb, RRDa
O
Ring Relay Driver Output.
Connects an external centralized ring generator to the sub-
scriber loop.
31, 48
GPOb, GPOa
O
General Purpose Output Driver.
Used as a relay driver or as a second battery select pin when
using a third battery supply.
32, 49
BATSELb,
BATSELa
O
Battery Voltage Select Pin.
Switches between high and low external battery supplies.
35
DRX
I
Receive PCM Data.
Input data from PCM/GCI bus.
36
DTX
O
Transmit PCM Data.
Output data to PCM/GCI bus.
39
PCLK
I
PCM Bus Clock.
Clock input for PCM/GCI bus timing.
33
RESET
I
Reset.
Active low. Hardware reset used to place all control registers in
a known state. An internal pulldown resistor asserts this pin low
when not driven externally.
34
FSYNC
I
Frame Sync.
8 kHz frame synchronization signal for PCM/GCI bus. May be
short or long pulse format.
40
INT
O
Interrupt.
Maskable interrupt output. Open drain output for wire-ORed
operation.
43
SCLK
I
Serial Port Bit Clock Input.
Controls serial data on SDO and latches data on SDI.
44
SDO
O
Serial Port Data Out.
Serial port control data output.
45
SDI
I
Serial Port Data In.
Serial port control data input.
Pin Number(s)
Symbol
Input/
Output
Description
Si3220
Si3225
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