The Si3220-based Dual ProSLIC
參數(shù)資料
型號(hào)： SI3225PPT0-EVB
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 59/112頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL W/SI3200 INTERFACE
標(biāo)準(zhǔn)包裝： 1
系列： ProSLIC®
類型： ADC + DAC，編碼解碼器，前端
適用于相關(guān)產(chǎn)品： Si3225
所含物品： 評(píng)估板和光盤
Si3220/25 Si3200/02
50
Rev. 1.3
Not
Recommended
fo
r N
ew
D
esi
gn
s
3.12. Ringing Generation
The Si3220-based Dual ProSLIC chipset provides a
balanced ringing waveform with or without dc offset.
The ringing frequency, cadence, waveshape, and dc
offset are register-programmable.
Using a balanced ringing scheme, the ringing signal is
applied to both the TIP and the RING lines using ringing
waveforms that are 180° out of phase with each other.
The resulting ringing signal seen across TIP-RING is
twice the amplitude of the ringing waveform on either
the TIP or the RING line, which allows the ringing
circuitry to withstand half the total ringing amplitude
seen across TIP-RING.
Figure 23. Balanced Ringing
An internal ringing scheme provides >40 Vrms into a 5
REN load at the terminal equipment using a user-
provided ringing battery supply. The specific ringing
supply voltage required depends on the desired ringing
voltage.
The
ringing
amplitude
at
the
terminal
equipment also depends on the loop impedance and
the load impedance in REN. The simplified circuit in
shows
the
relationship
between
loop
impedance and load impedance.
Figure 24. Simplified Loop Circuit During
Ringing
The following equation can be used to determine the
TIP-RING ringing amplitude required for a specific load
and loop condition:
where
and
When ringing longer loop lengths, adding a dc offset
voltage is necessary to reliably detect a ring trip
condition (off-hook phone). Adding dc offset to the
ringing signal decreases the maximum possible ringing
amplitude. Adding significant dc offset also increases
the power dissipation in the Si3200/2 and may require
additional airflow or modified PCB layout to maintain
acceptable operating temperatures in the line feed
circuitry. The Dual ProSLIC chipset automatically
applies and removes the ringing signal during VOC-
crossing periods to reduce noise and crosstalk to
adjacent lines. Table 29 provides a list of registers
required for internal ringing generation
RING
TIP
V
RING
V
TIP
SLIC
V
OFF
GND
V
TIP
V
RING
V
BATH
V
PK
V
OV
V
CM
V
OFF
R
LOOP
V
RING
R
LOAD
V
TERM
+
–
R
OUT
V
TERM
V
RING
R
LOAD
R
LOAD
R
LOOP
R
OUT
++
---------------------------------------------------------------------
=
R
LOOP
0.09
per foot for 26AWG wire
=
R
OUT
320
=
R
LOAD
7000
#REN
--------------------
=
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參數(shù)描述
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