PSLEEP Sl" />
參數(shù)資料
型號(hào)： SI3225PPT0-EVB
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 91/112頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL W/SI3200 INTERFACE
標(biāo)準(zhǔn)包裝： 1
系列： ProSLIC®
類(lèi)型： ADC + DAC，編碼解碼器，前端
適用于相關(guān)產(chǎn)品： Si3225
所含物品： 評(píng)估板和光盤(pán)
Si3220/25 Si3200/02
8
Rev. 1.3
Not
Recommended
fo
r N
ew
D
esi
gn
s
Chipset Power
Consumption
PSLEEP
Sleep mode, RESET = 0,
VBAT = –70 V
—8—
mW
POPEN
Open (high-impedance), VBAT =–70 V
—
69
—
mW
PSTBY
Active on-hook standby, VBAT = –70 V
—
89
—
mW
PACTIVE
3
Forward/reverse active off-hook,
ABIAS = 4 mA, VBAT = –24 V
—
267
—
mW
POHT
Forward/reverse OHT, OBIAS = 4 mA,
VBAT = –70 V
—
757
—
mW
PRING
Ringing, VRING =45vrms,
VBAT = –70 V, 1 REN load
—
541
—
mW
Table 3. 3.3 V Power Supply Characteristics1 (Continued)
(VDD, VDD1 – VDD4 = 3.3 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Notes:
1. All specifications are for a single channel based on measurements with both channels in the same operating state.
2. See "3.14.4. Ringing Power Considerations" on page 54 for current and power consumption under other operating
conditions.
3. Power consumption does not include additional power required for dc loop feed. Total system power consumption must
include an additional (VDD + |VBAT|) x ILOOP term.
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