Si3220/25 Si3200/02
92
Rev. 1.3
Not
Recommended
fo
r N
ew
D
esi
gn
s
3.31.3. Programming the Dual ProSLIC Using the
Monitor Channel
The Dual ProSLIC devices use the monitor channel to
Transfer status or operating mode information to and
from the host processor. Communication with the Dual
ProSLIC should be in the following format:
Byte 1: Device Address Byte
Byte 2: Command Byte
Byte 3: Register Address Byte
Bytes 4-n: Data Bytes
Bytes n+1, N+2: EOM
3.31.4. Device Address Byte
The device address byte identifies which device
receives the particular message. This address must be
the first byte sent to the Dual ProSLIC at the beginning
of each transmission sequence. The device address
byte has the following structure:
A = 1:
Channel A receives the command.
A = 0:
Channel A does not receive the command.
B = 1:
Channel B receives the command.
B = 0:
Channel B does not receive the command.
C = 1:
Normal command follows.
C = 0:
Channel identification command.
When C = 1, bits A and B are channel enable bits.
When these bits are set to 1, the corresponding
channels receive the command in the next command
byte. The channels with corresponding bits set to 0
ignore the subsequent command byte.
3.31.5. Channel Identification (CID) Command
The lowest programmable bit of the device address
byte, C, enables a special channel identification
command to identify itself by software. When C = 0, the
structure of this command is as follows:
A = 1: Channel A is the destination
A = 0: Channel B is the destination
Immediately after the last bit of the CID command is
received, the Dual ProSLIC responds with a fixed two-
byte identification code as follows:
A = 1: Channel A is the source
A = 0: Channel B is the source
Upon sending the two-byte CID command, the Dual
ProSLIC sends an EOM signal (MR = MX = 1) for two
consecutive frames. When C = 0, B must be 0, or the
Dual ProSLIC signals an abort due to an invalid
command. In this mode, only bit C is programmable.
3.31.6. Command Byte
The command byte has the following structure:
RW = 1: A Read operation is performed from the Dual
ProSLIC
RW = 0: A Write operation is performed to the Dual
ProSLIC
CMD[6:0] = 0000001: Read or Write from the Dual
ProSLIC
CMD[6:0] = 0000010-1111111: Reserved
3.31.7. Register Address Byte
The register address byte has the following structure:
This byte contains the actual 8-bit address of the
register to be read or written.
3.31.8. SC Channel
The downstream and upstream SC channels are
continuously carrying I/O information to and from the
Dual ProSLIC during every frame. The upstream
processor has immediate access to the receive
(downstream) and transmit (upstream) data present on
the Dual ProSLIC digital I/O port when used in GCI
mode. The SC channel consists of six C/I bits and two
handshaking bits as described in the tables below. The
functionality of the handshaking bits is defined in the
MSB
LSB
7
6
54
32
1
0
10
0
A
B
0
C
MSB
LSB
Bit
7
65
4
3 21
0
Address Byte
1
0 0 A 0 0 0
0
Command Byte
0
0 0
0
0 0 0
0
MSB
LSB
Bit
7
65
4
321
0
Address Byte
1
0 0
A
0 0 0
0
Command Byte
1
0 1
1
1 1 1
0
MSB
LSB
RW
CMD[6:0]
MSB
LSB
ADDRESS[7:0]