Philips Semiconductors
Objective specification
SC28L202
Dual UART
2000 Feb 10
52
REGISTER MAP (BASED ON 28L92)
NOTE: The register maps for channels A and B (UARTs A and B) contain some control registers that configure the entire chip.
These are
denoted by a ”
” symbol
A(6:0)
READ
EXTENSION
010 0000 (0x20)
Mode Register 0 (MR0 A)
NEW ADDRESS
010 0001 (0x21)
Mode Register 1 (MR1 A)
NEW ADDRESS
010 0010 (0x22)
Mode Register 2 (MR2 A)
NEW ADDRESS
010 0011 (0x23)
Mode Register 3 (MR3 A)
NEW ADDRESS
010 0100 (0x24)
Counter/Timer Clock Source (CTCS 0)
010 0101 (0x25)
Interrupt Status Register (ISR A)
010 0110 (0x26)
Programmable BRG Preset Lower (PBRGPL 0)
010 0111 (0x27)
Programmable BRG Preset Upper (PBRGPU 0)
WRITE
Mode Register 0 (MR0 A)
NEW ADDRESS
Mode Register 1 (MR1 A)
NEW ADDRESS
Mode Register 2 (MR2 A)
NEW ADDRESS
Mode Register 3 (MR3 A)
NEW ADDRESS
Counter/Timer Clock Source (CTCS 0)
Interrupt Mask Register (IMR A)
Programmable BRG Preset Lower (PBRGPL 0)
Programmable BRG Preset Upper (PBRGPU 0)
010 1000 (0x28)
010 1001 (0x29)
010 1010 (0x2A)
010 1011 (0x2B)
010 1100 (0x2C)
010 1101 (0x2D)
010 1110 (0x2E)
010 1111 (0x2F)
Mode Register 0 (MR0 B)
NEW ADDRESS
Mode Register 1 (MR1 B)
NEW ADDRESS
Mode Register 2 (MR2 B)
NEW ADDRESS
Mode Register 3 (MR3 B)
NEW ADDRESS
Counter/Timer Clock Source (CTCS 1)
Interrupt Status Register (ISR B)
Mode Register 0 (MR0 B)
NEW ADDRESS
Mode Register 1 (MR1 B)
NEW ADDRESS
Mode Register 2 (MR2 B)
NEW ADDRESS
Mode Register 3 (MR3 B)
NEW ADDRESS
Counter/Timer Clock Source (CTCS 1)
Interrupt Mask Register (IMR B)
011 0000 (0x30)
011 0001 (0x31)
011 0010 (0x32)
011 0011 (0x33)
011 0100 (0x34)
011 0101 (0x35)
011 0110 (0x36)
011 0111 (0x37)
Receiver Clock Select Register (RxCSR A)
Transmitter Clock Select Register (TxCSR A)
Input Port Change Interrupt Enable (IPCE A)
Programmable BRG Clock Source (PBRGCS)
Receiver Clock Select Register (RxCSR A)
Transmitter Clock Select Register (TxCSR A)
Input Port Change Interrupt Enable (IPCE A)
Programmable BRG Clock Source (PBRGCS)
Programmable BRG Preset Lower (PBRGPL 1)
Programmable BRG Preset Upper (PBRGPU 1)
Programmable BRG Preset Lower (PBRGPL 1)
Programmable BRG Preset Upper (PBRGPU 1)
011 1000 (0x38)
011 1001 (0x39)
011 1010 (0x3A)
011 1011 (0x3B)
011 1100 (0x3C)
011 1101 (0x3D)
011 1110 (0x3E)
011 1111 (0x3F)
Receiver Clock Select Register (RxCSR B)
Transmitter Clock Select Register (TxCSR B)
Input Port Change Interrupt Enable (IPCE B)
Receiver Clock Select Register (RxCSR B)
Transmitter Clock Select Register (TxCSR B)
Input Port Change Interrupt Enable (IPCE B)