參數(shù)資料
型號: SC28L202
廠商: NXP Semiconductors N.V.
英文描述: Dual universal asynchronous receiver/transmitter DUART
中文描述: 雙路通用異步接收器/發(fā)送器杜阿爾特
文件頁數(shù): 51/77頁
文件大?。?/td> 531K
代理商: SC28L202
Philips Semiconductors
Objective specification
SC28L202
Dual UART
2000 Feb 10
45
CSR A – Channel A Clock Select Register CSR A [7:4] –
Channel A Receiver Clock Select
This field selects the baud rate clock for the Channel A receiver. The
field definition is shown in Table 13.
CSR Clock Select Register
Bit 7
RECEIVER CLOCK SELECT
See Text and Table 13
BIT 6
BIT 5
BIT 4
BIT 3
TRANSMITTER CLOCK SELECT
See Text and Table 13
BIT 2
BIT 1
BIT 0
CSR A & CSR B
Table 13. Baud Rate (Base on a 14.7456 MHz crystal clock)
MR0[0] = 0 (Normal Mode)
CSR A [7:4]
ACR[7] = 0
ACR[7] = 1
0000
50
75
0001
110
110
0010
134.5
134.5
0011
200
150
0100
300
300
0101
600
600
0110
1,200
1,200
0111
1,050
2,000
1000
2,400
2,400
1001
4,800
4,800
1010
7,200
1,800
1011
9,600
9,600
1100
38.4K
19.2K
1101
Timer
Timer
1110
I/O4 A–16X
I/O4 A–16X
1111
I/O4 A–1X
I/O4 A–1X
MR0[0] = 1 (Extended Mode I)
ACR[7] = 0
300
110
134.5
1200
1800
3600
7200
1,050
14.4K
28.8K
7,200
57.6K
230.4K
Timer
I/O4 A–16X
I/O4 A–1X
MR0[2] = 1 (Extended Mode II)
ACR[7] = 0
4,800
880
1,076
19.2K
28.8K
57.6K
115.2K
1,050
57.6K
4,800
57.6K
9,600
38.4K
Timer
I/O4 A–16X
I/O4 A–1X
ACR[7] = 1
450
110
134.5
900
1800
3600
7,200
2,000
14.4K
28.8K
1,800
57.6K
115.2K
Timer
I/O4 A–16X
I/O4 A–1X
ACR[7] = 1
7,200
880
1,076
14.4K
28.8K
57.6K
115.2K
2,000
57.6K
4,800
14.4K
9,600
19.2K
Timer
I/O4 A–16X
I/O4 A–1X
NOTE: The receiver clock is always a 16X clock except for CSR A [7:4] = 1111.
CSR A [3:0] – Channel A EXTERNAL Transmitter Clock Select
This field selects the baud rate clock for the Channel A transmitter.
The field definition is as shown in Table 13, except as follows:
CSR A [3:0]
ACR[7] = 0
1110
I/O3 A–16X
1111
I/O3 A–1X
ACR[7] = 1
I/O3 A–16X
I/O3 A–1X
The transmitter clock is always a 16X clock except for CSR[3:0] =
1111.
CSR B [7:4] – Channel B Receiver Clock Select
This field selects the baud rate clock for the Channel B receiver. The
field definition is as shown in Table 13, except as follows:
CSR B [7:4]
ACR[7] = 0
1110
I/O6 A–16X
111
I/O6 A–1X
ACR[7] = 1
I/O6 A–16X
I/O6 A–1X
The receiver clock is always a 16X clock except for CSR B [7:4] =
1111.
CSR B [3:0] – Channel B Transmitter Clock Select
This field selects the baud rate clock for the Channel B transmitter.
The field definition is as shown in Table 13, except as follows:
CSR B [3:0]
ACR[7] = 0
1110
I/O5 A–16X
1111
I/O5 A–1X
ACR[7] = 1
I/O5 A–16X
I/O5 A–1X
The transmitter clock is always a 16X clock except for CSR B [3:0] =
1111.
Rx FIFO Register.
For characters shorter than 8 bits the unused bits are set to zero
Bit 7
BIT 6
Bits of the received data characters.
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Tx FIFO register.
For characters shorter than 8 bits the unused bits are set to zero
Bit 7
BIT 6
Bits of the data characters to be transmitted
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CR A and B Command Register
CR, one for each channel, controls the channel commands and
enables/disables the receiver and transmitter. Commands may be to
the upper and lower four bits in the same bus cycle. If both enable
and disable bits are set to 1 in the lower four bits a disable will
result.
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