參數(shù)資料
型號(hào)： SC28L202
廠商： NXP Semiconductors N.V.
英文描述： Dual universal asynchronous receiver/transmitter DUART
中文描述： 雙路通用異步接收器/發(fā)送器杜阿爾特
文件頁(yè)數(shù)： 26/77頁(yè)
文件大?。?/td> 531K
代理商： SC28L202
Philips Semiconductors
Objective specification
SC28L202
Dual UART
2000 Feb 10
20
REGISTER DESCRIPTION AND PROGRAMMING
NOTE
Programmers may use either of two register sets or mix the features
of each. It is suggested that only the extended register set be used
in new designs. However if a system needed to use a block of
communications code written for an older system then that code
could merely be called. This is similar to calling a DOS
program in
a WINDOWS
environment. Before calling legacy code it is
recommended (but not required) to execute “Reset to C92”
command. Also consideration must be given to the I/O pins to avoid
contention of drivers of the pins and an external driver.
Two control register descriptions and maps are implemented in the
SC28L92: one represents the previous 4–bit address and the other
the new 7–bit address space representing the all the new features of
the new design.
The Design of the SC28L202 allows for high degree with former
Philips two channel communications controllers – DUARTs. To
facilitate this feature the complete register function and control of the
SC26C92 is replicated in the SC28L202. That is code written for the
SCN2681, SCN68681, SCC2692, SCC68692 and SC26C92 will
operate with this device.
With the execution of code written for previous DUARTs and
immediately after a hardware reset or a “Reset to C92” command
the following configuration will exist:
1. The size of all FIFOs is set to 8 bytes (for legacy code).
2. FIFO interrupt levels are controlled by the bits of the MR
registers
3. All I/O ports are set to input.
4. Receiver FIFO set to interrupt on FIFO ready.
5. Transmitter FIFO set to interrupt on FIFO empty.
6. Baud selection follows previous 4 bit programming and baud rate
grouping controlled by the MR and ACR registers.
Table 2. SC28L202 REGISTER BIT DESCRIPTIONS
Registers that control Global Properties of the 28L202
GCCR – Global Configuration Control Register
THIS IS A VERY IMPORTANT REGISTER! IT SHOULD BE THE FIRST REGISTER ADDRESSED DURING INITIALIZATION.
Hex
Bit (7)
Bit (6)
Bit (5:3)
Bit(2:1)
BIT 0
Addr
Reserved
DACKN
Assertion
Reserved
IVC Interrupt Vector Control
ISR Read Mode
0 – Slow (timed
by 2 SCLK
edges)
1 – Fast
(Asynchronous)
Set to 0
00 = no interrupt vector
01 = IVR(7:0)
10 = IVR(7:1) + channel code
11 = IVR(7:5) + interrupt type + channel code
0 = ISR Unmasked
1 = ISR Read Masked by IMR
GCCR(7:6) DACKN Assertion
Motorola bus cycle time can be controlled by selecting a DACKN
assertion time based on X1/Sclk speed .
See examples below.
X1/SCLK
#SCLK Cycles
Delay
3.6864 MHz
1/2–1
136–272 ns
7.3728 MHz
1/2–1
68–136 ns
14.7456 MHz
1/2–1
34–68 ns
29.4912 MHz
1–2
34–68 ns
33.1776 MHz
2–3
60–90 ns
44.2368 MHz
2–3
46–68 ns
GCCR(5:3): Reserved
GCCR(2:1): Interrupt vector configuration
The IVC field controls if and how the assertion of IACKN (the
interrupt acknowledge pin) will form the interrupt vector for the
DUART. If b’00, no vector will be presented during an IACKN cycle.
The bus will be driven high (0xFF). If the field contains a b’01, the
contents of the IVR, Interrupt Vector Register, will be presented as
the interrupt vector without modification.
If IVC = 0x10, the channel code will replace the LSB of the IVR; if
IVC = b’11 then a modified interrupt type and channel code replace
the 3 LSBs of the IVR.
NOTE
: The modified type field IVR(2:1) is:
10 Receiver w/o error
11 Receiver with error
01 Transmitter
00 All remaining sources
GCCR(0): Interrupt Status Masking
This bit controls the readout mode of the Interrupt Status Register,
ISR. If set, the ISR reads the current status masked by the IMR, i.e.
only interrupt sources enabled in the IMR can ever show a ’1’ in the
ISR. If cleared, the ISR shows the current status of the interrupt
source without regard to the Interrupt Mask setting.
SFSR A and B Special Feature & Status Register
Bit 7
Bit 6
Bit 5
BIT 4
BIT 3
BIT 2:1
BIT 0
Reserved
Reserved
Reserved
Reserved
Loop Back Error
Remote Loop Error Check
Reserved
0 = No
1 = Yes
(read Only)
00 = Disabled
01 = Enabled, RxC
TxC
10 = Enabled, RxC
TxCN
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相關(guān)代理商/技術(shù)參數(shù)
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SC28L202A1 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual universal asynchronous receiver/transmitter DUART
SC28L202A1B 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual universal asynchronous receiver/transmitter DUART
SC28L202A1D 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual universal asynchronous receiver/transmitter DUART
SC28L202A1DGG 功能描述:UART 接口集成電路 3-5V 2CH UART 3MBPS 256B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC28L202A1DGG,112 功能描述:UART 接口集成電路 3-5V 2CH UART 3MBPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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