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參數(shù)資料
| 型號： | SC28L202 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Dual universal asynchronous receiver/transmitter DUART |
| 中文描述： | 雙路通用異步接收器/發(fā)送器杜阿爾特 |
| 文件頁數(shù)： | 52/77頁 |
| 文件大?。?/td> | 531K |
| 代理商： | SC28L202 |
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Philips Semiconductors
Objective specification
SC28L202
Dual UART
2000 Feb 10
46
CR Command Register
Bit 7
MISCELLANEOUS COMMANDS
See Text of Channel Command Register
BIT 6
BIT 5
BIT 4
BIT 3
Disable Tx
1 = Yes
0 = No
BIT 2
Enable Tx
1 = Yes
0 = No
BIT 1
Disable Rx
1 = Yes
0 = No
BIT 0
Enable Rx
1 = Yes
0 = No
CR A &CR B
NOTE: Access to the miscellaneous commands should be separated by 3 X1 clock edges. A disabled transmitter cannot be loaded.
COMMAND REGISTER TABLE A and B
Commands 0xE, 0xF (marked with *) are global and exist only in channel A’s register space.
Channel Command Code
Channel Command
CR[7:4]
Description
0000
NOP
0001
Set MR pointer to 1
0010
Reset Receiver
0011
Reset Transmitter
0100
Reset Error Status
0101
Reset Break Change Interrupt
0110
Begin Transmit Break
0111
End Transmit Break
Channel Command Code
CR[7:4]
1000
1001
1010
1011
1100
1101
1110
1111
Channel Command
Description
Assert RTSN (I/O0 B or I/O1 B)
Negate RTSN (I/O0 B or I/O1 B)
Set C/T Receiver time–out mode on
Set MR pointer to 0
Set C/T Receiver time–out mode off
Block Error Status on RxFIFO load
Power Down Mode On
Disable Power Down Mode
0000 No command.
0001 set MR pointer to 1
0010 Reset receiver. Immediately resets the receiver as if
hardware reset had been applied. The receiver is reset and the
FIFO pointer is reset to the first location effectively discarding all
unread characters in the FIFO.
0011 Reset transmitter. Immediately resets the transmitter as if a
hardware reset had been applied. The transmitter is reset and the
FIFO pointer is reset to the first location effectively discarding all
untransmitted characters in the FIFO.
0100 Reset error status. Clears the received break, parity error,
framing error, and overrun error bits in the status register
(SR[7:4]). I
It is used in either character or block mode. In block mode it would
normally be used after the block is read.
0101 Reset break change interrupt. Causes the break detect
change bit in the interrupt status register (ISR[2]) to be cleared to
zero.
0110 Start break. Forces the TxD output low (spacing). If the
transmitter is empty, the start of the break condition will be
delayed up to two bit times. If the transmitter is active and the
TxFIFO is empty then the break begins when transmission of the
current character is completed. If there are characters in the
TxFIFO, the start of break is delayed until all characters presently
in the TxFIFO and any subsequent characters loaded have been
transmitted. (Tx Idle must be true before break begins).
The transmitter must be enabled to start a break.
0111 Stop break. The TxD line will go high (marking) within two bit
times. TxD will remain high for one bit time before the next
character is transmitted.
1000 Assert RTSN. Causes the RTSN output to be asserted (low).
1001 Negate RTSN. Causes the RTSN output to be negated
(high).
NOTE
: The two commands above actually reset and set,
respectively, the I/O0 B or I/O1 B pin associated WITH the
OPR register.
1010 Set C/T Receiver time out mode on. The receiver in this
channel will restart the C/T as reach receive character is
transferred from the shift register to the RxFIFO. The C/T is
placed in the Counter Mode, the Start/Stop Counter commands
are disabled, the counter is stopped and the Counter Ready bit,
ISR(3), is reset.
1011 Set MR Pointer to 0
1100 Set C/T Receiver time out mode off
1101 Block error status accumulation on FIFO entry. Allows the
“received break”, “framing error” and “parity error” bits to be set as
the received character is loaded to the RxFIFO. (normally these
bits are set on reading of the data from the RxFIFO) Setting this
mode can give information about error data up to 256 bytes earlier
than the normal mode. However it clouds the ability to know
precisely which byte(s) are in error.
1110 Power Down Mode On
1111 Disable Power Down Mode
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SC28L202A1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual universal asynchronous receiver/transmitter DUART |
| SC28L202A1B | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual universal asynchronous receiver/transmitter DUART |
| SC28L202A1D | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual universal asynchronous receiver/transmitter DUART |
| SC28L202A1DGG | 功能描述:UART 接口集成電路 3-5V 2CH UART 3MBPS 256B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC28L202A1DGG,112 | 功能描述:UART 接口集成電路 3-5V 2CH UART 3MBPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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