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參數(shù)資料
| 型號(hào)： | SC28L202 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Dual universal asynchronous receiver/transmitter DUART |
| 中文描述： | 雙路通用異步接收器/發(fā)送器杜阿爾特 |
| 文件頁數(shù)： | 53/77頁 |
| 文件大小： | 531K |
| 代理商： | SC28L202 |
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Philips Semiconductors
Objective specification
SC28L202
Dual UART
2000 Feb 10
47
IPCR Input Port Configuration Register
Bit 7
IPCR
Delta
I/O 3A
0 = no change
1 = change
BIT 6
Delta
I/O 2A
0 = no change
1 = change
BIT 5
Delta
I/O 1A
0 = no change
1 = change
BIT 4
Delta
I/O 0A
0 = no change
1 = change
BIT 3
I/O 3A
BIT 2
I/O 2A
BIT 1
I/O 1A
BIT 0
I/O 0A
0 = low
1 = High
0 = low
1 = High
0 = low
1 = High
0 = low
1 = High
IPCR [7:4] I/03A, I/O2 A, I/O1 A, I/O0 A Change–of–State
These bits are set when a change–of–state, as defined in the input
port section of this data sheet, occurs at the respective input pins.
They are cleared when the IPCR is read by the CPU. A read of the
IPCR also clears ISR [7], the input change bit in the interrupt status
register. The setting of these bits can be programmed to generate
an interrupt to the CPU.
IPCR [3:0] I/O3 A, I/O2 A, I/O1 A, I/O0 A logical level of I/O pin.
These bits provide the current state of the respective inputs. The
information is unlatched and reflects the state of the input pins at the
time the IPCR is read.
ACR Auxiliary Control Register
Bit 7
BRG SET
Select
BIT 6
Counter Timer Mode
and
clock source select
See Table 14
BIT 5
BIT 4
BIT 3
Delta
I/O3 A interrupt
enable
0 = off
1 = enabled
BIT 2
Delta
I/O2 A interrupt
enable
0 = off
1 = enabled
BIT 1
Delta
I/O1 A interrupt
enable
0 = off
1 = enabled
BIT 0
Delta
I/O0 A interrupt
enable
0 = off
1 = enabled
ACR
0 = set 1
1 = set 2
ACR[7] – Baud Rate Generator Set Select
This bit selects one of two sets of baud rates to be generated by the
BRG and it effects both channels. (see Table 13).
ACR[6:4] – Counter/Timer Mode And Clock Source Select
This field selects the operating mode of the counter/timer and its
clock source as shown in Table 14.
ACR [3:0] – I/O3 A, I/O2 A, I/O1 A, I/O0 A Change–of–State
Interrupt Enable
This field selects which bits of the input port change register (IPCR)
cause the input change bit in the interrupt status register (ISR [7]) to
be set. If a bit is in the ‘on’ state the setting of the corresponding bit
in the IPCR will also result in the setting of ISR [7], which results in
the generation of an interrupt output if IMR [7] = 1. If a bit is in the
‘off’ state, the setting of that bit in the IPCR has no effect on ISR [7].
Table 14. ACR 6:4 Field Definition
ACR(6:4)
MODE
000
Counter
001
Counter
CLOCK SOURCE
External (I/02A)
TxC A – 1X clock of Channel A
transmitter
TxC B – 1X clock of Channel B
transmitter
(X1/Sclk) clock divided by 16
External (I/O 2A)
External (I/O2 A) divided by 16
Crystal or external clock (X1/Sclk)
(X1/Sclk) clock divided by 16
010
Counter
011
100
101
110
111
NOTE: The timer mode generates a square wave.
Counter
Timer
Timer
Timer
Timer
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相關(guān)代理商/技術(shù)參數(shù) |
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| SC28L202A1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual universal asynchronous receiver/transmitter DUART |
| SC28L202A1B | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual universal asynchronous receiver/transmitter DUART |
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| SC28L202A1DGG | 功能描述:UART 接口集成電路 3-5V 2CH UART 3MBPS 256B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC28L202A1DGG,112 | 功能描述:UART 接口集成電路 3-5V 2CH UART 3MBPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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