參數(shù)資料
型號(hào)： SAF82525
廠商： INFINEON TECHNOLOGIES AG
英文描述： Data Communications ICs
中文描述： 數(shù)據(jù)通信集成電路
文件頁數(shù)： 78/126頁
文件大?。?/td> 730K
代理商： SAF82525
Semiconductor Group
78
SAB 82525
SAB 82526
SAF 82525
SAF 82526
After the DMA controller has been set up for the reception of the next frame, the CPU must be
issue a RMC command to acknowledge the completion of the receive frame processing.
The HSCX will not initiate further DMA cycles by activating the DRQR line prior to the reception
of RMC.
Note:
It’s also possible to set up the DMA controller immediately after the start of a frame has
been detected using the HSCX’s RFS (Receive Frame Start) interrupt option (
see
chapter 4.3
).
The following figure gives an example of a DMA controlled reception sequence, supposed that
a long frame (66 bytes) followed by two short frames (6 bytes each) are received.
Figure 38
DMA Driven Reception Sequence Example
Serial
Interface
HSCX
CPU/DMA
Interface
ITD00252
RME
32
32
2
6
RF2
RMC
Receive Frame
(66
Bytes)
DMA Read Cycles (68)
DRQR(8)
. . .
. . .
DRQR(8)
RD
. . .
DRQR(4)
DRQR(32)
. . .
RD
RD
RD
RD
. . .
DRQR(32)
RF3
6
R
1
RD
RD
RME
RMC
RD
RD
RD
RME
RMC
R
R
相關(guān)PDF資料
PDF描述
SAB82525N Data Communications ICs
SAB82526 Data Communications ICs
SAB82526N Data Communications ICs
SAF82525N Data Communications ICs
SAF82526 Data Communications ICs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SAF82525HV2.2 制造商:Lantiq 功能描述:
SAF82525HV22XP 制造商:Lantiq 功能描述:HSCX
SAF82525HV22XT 制造商:Lantiq 功能描述:HSCX
SAF82525N 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Data Communications ICs
SAF82525NV2.1 制造商:Infineon Technologies AG 功能描述:
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