- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374697 > SAF82525 (INFINEON TECHNOLOGIES AG) Data Communications ICs PDF資料下載
參數(shù)資料
| 型號(hào)： | SAF82525 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | Data Communications ICs |
| 中文描述： | 數(shù)據(jù)通信集成電路 |
| 文件頁數(shù)： | 67/126頁 |
| 文件大小： | 730K |
| 代理商： | SAF82525 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁當(dāng)前第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁
Semiconductor Group
67
SAB 82525
SAB 82526
SAF 82525
SAF 82526
6.5 One Bit Insertion
Similar to the zero bit insertion (bit-stuffing) mechanism, as defined by the HDLC protocol, the
HSCX offers a completely new feature of inserting/deleting a one after seven consecutive
zeros in the transmit/receive data stream, if the serial channel is operating in a bus
configuration.
This method is profitable if clock recovery should be performed by DPLL.
Since only NRZ data encoding is supported in a bus configuration (
see chapter 5.4
), there are
possibly long sequences without edges in the receive data stream in case of successive "0"-s
received, and the DPLL may loose synchronization.
Using the one bit insertion feature by setting the OIN bit in the CCR1 register, however, it is
guaranteed that at least after
– 5 consecutive "1"-s a "0" will appear (bit-stuffing), and
– 7 consecutive "0"-s a "1" will appear (one insertion)
and thus a correct function of the DPLL is ensured.
Note:
As with the bit-stuffing, this method is fully transparent to the user, but it is not in
accordance with the HDLC protocol, i.e. it can only be applied in private systems using
HSCX circuits exclusively.
6.6 Data Inversion
When NRZ data encoding has been selected, the HSCX may transmit and receive data
inverted, i.e. a
"one" bit is transmitted as phys. zero (0 V) and a "zero" bit as phys. one (+ 5 V) via the T
×
D line.
This feature is selected by setting the DIV bit in the CCR2 register.
Please note that data cannot be inverted in bus mode unless you invert the T
×
D / R
×
D signal
before it is sent into C
×
D.
ITD00245
Transmit
Receive
Log. Data Bit
1
0
Phys. Level
5
0
V
V
+
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAB82525N | Data Communications ICs |
| SAB82526 | Data Communications ICs |
| SAB82526N | Data Communications ICs |
| SAF82525N | Data Communications ICs |
| SAF82526 | Data Communications ICs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAF82525HV2.2 | 制造商:Lantiq 功能描述: |
| SAF82525HV22XP | 制造商:Lantiq 功能描述:HSCX |
| SAF82525HV22XT | 制造商:Lantiq 功能描述:HSCX |
| SAF82525N | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Data Communications ICs |
| SAF82525NV2.1 | 制造商:Infineon Technologies AG 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。