參數(shù)資料
型號: SAA7378GP
廠商: NXP Semiconductors N.V.
英文描述: Single Chip Digital Servo Processor and Compact Disc Decoder
中文描述: 單片機(jī)數(shù)字伺服處理器和光盤解碼器
文件頁數(shù): 32/45頁
文件大小: 224K
代理商: SAA7378GP
Philips Semiconductors
Preliminary specification: Version 1.0
May 1995
32
Digital Servo Processor and Compact Disc Decoder (CD7)
SAA7378GP
REGISTER
ADDRESS
DATA
FUNCTION
INITIAL
9
1 0 0 1
0 0 1 1
0 0 0 1
0 0 1 0
0 1 0 0
0 1 0 1
x 0 1 0
x 0 1 1
x 1 1 0
x 1 1 1
0 x x x
1 x x x
0 0 x x
PLL loop filter equalisation
PLL 30ns over-equalisation
PLL 15ns over-equalisation
PLL 15ns under-equalisation
PLL 30ns under-equalisation
Level II clock accuracy (<1000ppm)
Level I clock accuracy (<50ppm)
Level III clock accuracy (>1000ppm)
EBU off - output low
Flags in EBU off
Flags in EBU on
33.8688MHz crystal present,
or 8.4672MHz crystal with SELPLL set high
16.9344MHz crystal present
Standby 1 : ’CD-STOP’ mode
Standby 2 : ’CD-PAUSE’ mode
Operating mode
External offtrack signal input at V1
Internal offtrack signal used (V1 may be read via status)
Kill-L at KILL output, Kill-R at V3 output
V3 = 0; single Kill output
V3 = 1; single Kill output
4-line motor (using V4, V5)
V4 = 0
V4 = 1
De-emphasis signal at V5, no internal de-emphasis filter
V5 = 0
V5 = 1
Motor brakes to 12%
Motor brakes to 6%
Reset
(PLL equalisation)
A
1 0 1 0
Reset
(EBU output)
Reset
B
1 0 1 1
Reset
0 1 x x
x x 0 0
x x 1 0
x x 1 1
x x x 1
x x x 0
x x 0 x
0 0 1 x
0 1 1 x
0 0 0 0
x x 1 0
x x 1 1
0 1 x x
1 0 x x
1 1 x x
0 1 0 0
0 1 0 1
Reset
C
1 1 0 0
(Versatile pins
interface)
Reset
Reset
D
1 1 0 1
(Versatile pins
interface)
Reset
Reset
Reset
E
1 1 1 0
Table 1 Registers 0 to E
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