參數(shù)資料
型號： SAA7378GP
廠商： NXP Semiconductors N.V.
英文描述： Single Chip Digital Servo Processor and Compact Disc Decoder
中文描述： 單片機數(shù)字伺服處理器和光盤解碼器
文件頁數(shù)： 16/45頁
文件大?。?/td> 224K
代理商： SAA7378GP
Philips Semiconductors
Preliminary specification: Version 1.0
May 1995
16
Digital Servo Processor and Compact Disc Decoder (CD7)
SAA7378GP
7.9
The biphasemark digital output signal at pin DOBM is according to the format defined by the IEC958 specification. The
DOBM pin can be held low; selected via register A:
EBU Interface
7.9.1
The digital audio output consists of 32-bit words ("subframes") transmitted in biphasemark code (two transitions for a logic’1’
and one transition for a logic’0’). Words are transmitted in blocks of 384.
Format
Sync:
The Sync word is formed by violation of the biphase rule and therefore does not contain any data. Its
length is equivalent to 4 data bits. The 3 different sync patterns indicate the following situations:
Sync B:- Start of a block (384 words), word contains left sample.
Sync M:- Word contains left sample (no block start).
Sync W:- Word contains right sample.
Audio sample: Left and right samples are transmitted alternately.
Validity flag:
Audio samples are flagged (bit 28 = ’1’) if an error has been detected but was uncorrectable. This flag
remains the same even if data is taken after concealment
User data:
Subcode bits Q until W from the subcode section are transmitted via the user data bit. This data is
asynchronous with the block rate.
Channel status: The channel status bit is the same for left and right words. Therefore a block of 384 words contains 192
channel status bits. The category code is always CD. The bit assignment is shown below.
7.10
The KILL circuit detects digital silence by testing for an all-zero or all-ones data word in the left or right channel before the
digital filter. The output is switched active-low when silence has been detected for at least 250ms, or if Mute is active. Two
modes are available, selected by register C:
-
1 pin kill:
KILL active low indicates silence detected on both left and right channels.
-
2 pin kill:
KILL active low indicates silence detected on left channel.
V3 active low indicates silence detected on right channel.
KILL Circuit
sync
bits 0 - 3
auxiliary
bits 4 - 7
Not used. Normally zero
error flags
bit 4
CFLG error and interpolation flags when selected by register A
audio sample
bits 8 - 27
First 4 bits not used (always zero). 2’s compliment. LSB = bit 12, MSB = bit 27
validity flag
bit 28
Valid = logic 0
user data
bit 29
Used for subcode data (Q to W)
channel status
bit 30
Control bits and category code
parity bit
bit 31
Even parity for bits 4 to 30
control
bits 0 - 3
copy of CRC checked Q-channel control bits 0 - 3;
bit 2 is logic 1 when copy permitted;
bit 3 is logic 1 when recording has preemphasis
reserved mode
bits 4 - 7
always zero.
category code
bits 8 - 15
CD: bit 8 = logic1, all other bits = logic 0
clock accuracy
bits 28 - 29
set by register A:
10 = level I
00 = level II
01 = level III
remaining
bits 16 - 27
bits 30 - 191
always zero
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