- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄372115 > SAA7378GP (NXP Semiconductors N.V.) Single Chip Digital Servo Processor and Compact Disc Decoder PDF資料下載
參數(shù)資料
| 型號： | SAA7378GP |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Single Chip Digital Servo Processor and Compact Disc Decoder |
| 中文描述： | 單片機數(shù)字伺服處理器和光盤解碼器 |
| 文件頁數(shù)： | 10/45頁 |
| 文件大小： | 224K |
| 代理商： | SAA7378GP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁當前第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁
Philips Semiconductors
Preliminary specification: Version 1.0
May 1995
10
Digital Servo Processor and Compact Disc Decoder (CD7)
SAA7378GP
7.3
The SAA7378 has an integrated slice level comparator which can be clocked by the crystal frequency clock, or 8 times the
crystal frequency clock (if SELPLL is set high while using an 8.4672MHz crystal, and register 4 is set to
0xxx
). The slice level
is controlled by an internal current source applied to an external capacitor under the control of the Digital Phase-Locked Loop
(DPLL)
.
Data Slicer and Clock Regenerator
Regeneration of the bit clock is achieved with an internal fully digital PLL. No external components are required and the bit
clock is not output. The PLL has two registers (8 and 9) for selecting bandwidth and equalization.
For certain applications an offtrackinput is necessary. This is internally connected from the servo part (its polarity can be
changed by the foc_parm1parameter), but may be input via the V1 pin if selected by register C. If this flag is high, the
SAA7378 will assume that its servo part is following on the wrong track, and will flag all incoming HF data as incorrect.
7.4
Demodulator
7.4.1
A double timing system is used to protect the demodulator from erroneous sync patterns in the serial data. The master
counter is only reset if:
-
a sync coincidence detected; sync pattern occurs 588
±
1 EFM clocks after the previous sync pattern.
-
a new sync pattern is detected within
±
6 EFM clocks of its expected position.
Frame Sync Protection
The sync coincidence signal is also used to generate the PLL lock signal, which is active high after 1 sync coincidence found,
and reset low if during 61 consecutive frames no sync coincidence is found. The PLL lock signal can be accessed via the
SDA or STATUS pins selected by register 2 and 7.
Also incorporated in the demodulator is a RL2 (Run Length 2) correction circuit. Every symbol detected as RL2 will be
pushed back to RL3. To do this the phase error of both edges of the RL2 symbol are compared and the correction is executed
at the side with the highest error probability.
7.4.2
T
he 14-bit EFM data and subcode words are decoded into 8-bit symbols.
EFM Demodulation
+
-
D Q
DPLL
crystal
clock
HFIN
HFREF
IREF
ISLICE
V
SS
V
DD
HF
input
2.2nF
2.2k
22k
47pF
22nF
V
SSA
V
SSA
V
DD
/2
100nF
100
μ
A
100
μ
A
Figure 4 Data Slicer Showing Typical Application Components
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA7380 | Error correction and host interface IC for CD-ROM ELM |
| SAA7380GP | Error correction and host interface IC for CD-ROM ELM |
| SAA7381 | ATAPI CD-R block decoder |
| SAA7382GP | Error correction and host interface IC for CD-ROM ELM |
| SAA7382 | Error correction and host interface IC for CD-ROM ELM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7380 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Error correction and host interface IC for CD-ROM ELM |
| SAA7380GP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Error correction and host interface IC for CD-ROM ELM |
| SAA7381 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:ATAPI CD-R block decoder |
| SAA7382 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Error correction and host interface IC for CD-ROM ELM |
| SAA7382GP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Error correction and host interface IC for CD-ROM ELM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。