參數(shù)資料
型號: SAA7378GP
廠商: NXP Semiconductors N.V.
英文描述: Single Chip Digital Servo Processor and Compact Disc Decoder
中文描述: 單片機(jī)數(shù)字伺服處理器和光盤解碼器
文件頁數(shù): 15/45頁
文件大?。?/td> 224K
代理商: SAA7378GP
Philips Semiconductors
Preliminary specification: Version 1.0
May 1995
15
Digital Servo Processor and Compact Disc Decoder (CD7)
SAA7378GP
7.8
The SAA7378 is compatible with a wide range of Digital-Analogue Converters. Six formats are supported and are shown
below. Figure 8 and Figure 9 show the Philips IIS and the EIAJ data formats respectively. All formats are MSB first and fs is
44.1kHz. The polarity of the WCLK and the data can be inverted; selectable by register 7.
DAC Interface
REGISTER 3
SAMPLE
FREQUENCY
No of
BITS
SCLK
MHz
FORMAT
INTERPOLATION
0000
4fs
16
8.4672 * n
EIAJ - 16 bits
yes
0100
4fs
18
8.4672 * n
EIAJ - 18 bits
Philips I
2
S - 18 bits
yes
1100
4fs
18
8.4672 * n
yes
0011
2fs
16
4.2336 * n
EIAJ - 16 bits
yes
0111
2fs
18
4.2336 * n
EIAJ - 18 bits
Philips I
2
S - 18 bits
yes
1111
2fs
18
4.2336 * n
yes
17
0
15
SCLK
DATA
WCLK
LEFT CHANNEL DATA (WCLK NORMAL POLARITY)
Figure 8
Philips I
2
S Data Format (18-Bit Word Length Shown
)
1
16
14
1 0
17
0
0
17
SCLK
DATA
WCLK
LEFT CHANNEL DATA
Figure 9 EIAJ Data Format (18-Bit Word Length Shown)
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