參數(shù)資料
型號: SAA7378GP
廠商: NXP Semiconductors N.V.
英文描述: Single Chip Digital Servo Processor and Compact Disc Decoder
中文描述: 單片機數(shù)字伺服處理器和光盤解碼器
文件頁數(shù): 31/45頁
文件大小: 224K
代理商: SAA7378GP
Philips Semiconductors
Preliminary specification: Version 1.0
May 1995
31
Digital Servo Processor and Compact Disc Decoder (CD7)
SAA7378GP
REGISTER
ADDRESS
DATA
FUNCTION
INITIAL
4
0 1 0 0
x 0 0 0
x 0 0 1
x 0 1 0
x 0 1 1
x 1 0 0
x 1 0 1
x 1 1 0
x 1 1 1
0 x x x
1 x x x
x x 0 0
x x 0 1
x x 1 0
x x 1 1
0 0 x x
0 1 x x
1 0 x x
x x 0 0
x x 0 1
x x 1 0
x x 1 1
0 0 x x
0 1 x x
1 0 x x
1 1 x x
x 0 0 0
x 1 0 0
0 x x x
1 x x x
Motor gain G = 3.2
Motor gain G = 4.0
Motor gain G = 6.4
Motor gain G = 8.0
Motor gain G = 12.8
Motor gain G = 16.0
Motor gain G = 25.6
Motor gain G = 32.0
Disable comparator clock divider
Enable comparator clock divider; only if SELLPLL set high
Motor f4 = 0.5Hz
Motor f4 = 0.7Hz
Motor f4 = 1.4Hz
Motor f4 = 2.8Hz
Motor f3 = 0.85Hz
Motor f3 = 1.71Hz
Motor f3 = 3.42Hz
Motor power max. 37%
Motor power max. 50%
Motor power max. 75%
Motor power max. 100%
MOTO1, MOTO2 pins tri-state
Motor PWM mode
Motor PDM mode
Motor CDV mode
DAC data normal value
DAC data inverted value
L channel first at DAC (WCLK normal)
R channel first at DAC (WCLK inverted)
Loop BW Hz
Int. BW Hz
1640
525
3279
263
6560
131
1640
1050
3279
525
6560
263
1640
2101
3279
1050
6560
525
1640
4200
3279
2101
6560
1050
Reset
(Motor gain)
Reset
5
0 1 0 1
Reset
(Motor bandwidth)
Reset
6
0 1 1 0
Reset
(Motor output
configuration)
Reset
7
0 1 1 1
Reset
(DAC output)
Reset
Low-pass BW Hz
8400
16800
33600
8400
16800
33600
8400
16800
33600
8400
16800
33600
8
1 0 0 0
0 0 0 0
0 0 0 1
0 0 1 0
0 1 0 0
0 1 0 1
0 1 1 0
1 0 0 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 0 1
1 1 1 0
(PLL loop filter
bandwidth)
Reset
Table 1 Registers 0 to E
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