參數(shù)資料
型號: SAA7378GP
廠商: NXP Semiconductors N.V.
英文描述: Single Chip Digital Servo Processor and Compact Disc Decoder
中文描述: 單片機(jī)數(shù)字伺服處理器和光盤解碼器
文件頁數(shù): 21/45頁
文件大?。?/td> 224K
代理商: SAA7378GP
Philips Semiconductors
Preliminary specification: Version 1.0
May 1995
21
Digital Servo Processor and Compact Disc Decoder (CD7)
SAA7378GP
8.
FUNCTIONAL DESCRIPTION OF THE SERVO PART
8.1
The photo detector in conventional two-stage three-beam compact disc systems normally contains six discrete diodes. Four
of these diodes (three for single focault systems) carry the central aperture (CA) signal while the other two diodes (satellite
diodes) carry the radial tracking information. The CA signal is processed into an HF signal (for the decoder function) and LF
signal (information for the focus servo loop) before it is supplied to the SAA7378.
Diode Signal Processing
The analog signals from the central and satellite diodes are converted into a digital representation using analog to digital
converters (ADCs). The ADCs are designed to convert unipolar currents into a digital code. The dynamic range of the input
currents is adjustable within a given range which is dependent on the value of external resistor connected to IREFT. The
maximum current for the central diodes and satellite diodes is given below:
I
in(max, central)
= (2.4 * 10
6
/ R
IREFT
)
μ
A
I
in(max, satellite)
= (1.2 * 10
6
/ R
IREFT
)
μ
A
The V
RH
voltage is internally generated by control circuitry which takes care that the V
RH
voltage is adjusted depending upon
the spread of internal capacitors, using the reference current generated by the external resistor on IREFT. In the application
V
RL
is connected to V
SSA1
. The maximum input currents for a range of resistors is given below:
This mode of V
RH
automatic adjustment can be selected by the preset latch command.
Alternatively the dynamic range of the input currents can be made dependent on the ADC reference voltages; V
RL
and V
RH
,
for this case the maximum current for the central diodes and satellite diodes is given below:
I
in(max, central)
= f
sys
* (V
RH
- V
RL
) * 1.0 * 10
-6
μ
A
I
in(max, satellite)
= f
sys
* (V
RH
- V
RL
) * 0.5 * 10
-6
μ
A where f
sys
= 4.2336MHz
V
RH
is generated internally, and there are 32 levels which can be selected under software control, via the preset latch
command. With this command the V
RH
voltage can be set to 2.5V then modified, decremented one level or incremented, by
resending the command the required number of times. In the application V
RL
is connected to V
SSA1
.
8.2
The digital codes retrieved from the ADCs are applied to logic circuitry to obtain the various control signals. The signals from
the central aperture diodes are processed to obtain a normalised focus error signal:
Signal Conditioning
R
IREFT
diode input current range
D1,D2,D3,D4
A)
10.909
R1,R2
A
)
5.455
220k
240k
10.000
5.000
270k
8.889
4.444
300k
8.000
4.000
330k
7.273
3.636
360k
6.667
3.333
390k
6.154
3.077
430k
5.581
2.791
470k
5.106
2.553
510k
4.706
2.353
560k
4.286
2.143
620k
3.871
1.935
D1 - D2
D1 + D2
FE
n
=
D3 - D4
D3 + D4
-
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