參數(shù)資料
型號: SAA5647HL
廠商: NXP Semiconductors N.V.
英文描述: Enhanced TV microcontrollers with On-Screen Display (OSD)(帶全屏顯示的增強型TV控制器)
中文描述: 與微控制器在強化電視屏幕顯示(OSD)(帶全屏顯示的增強型電視控制器)
文件頁數(shù): 45/112頁
文件大?。?/td> 436K
代理商: SAA5647HL
2000 Jun 30
45
Philips Semiconductors
Objective specification
Enhanced TV microcontrollers with
On-Screen Display (OSD)
SAA56xx
16.3.3
SAD DC C
OMPARATOR MODE
The SAD module (see Fig.11) incorporates a DC
Comparator mode, which is selected using the
‘DC_COMP’ control bit in the SADB SFR. This mode
enables the microcontroller to detect a threshold crossing
at the input to the selected analog input pin
(P3.0/ADC0, P3.1/ADC1, P3.2/ADC2 or P3.3/ADC3) of
the software ADC. A level sensitive interrupt is generated
when the analog input voltage level at the pin falls below
the analog output level of the SAD DAC.
This mode is intended to provide the device with a
wake-up mechanism from Power-down or Idle mode when
a key-press on the front panel of the TV is detected.
The following software sequence should be used when
utilizing this mode for Power-down or Idle mode:
1.
Disable INT1 using the IE SFR.
2.
Set INT1 to level sensitive using the TCON SFR.
3.
Set the DAC digital input level to the desired threshold
level using SAD/SADB SFRs and select the required
input pin (P3.0, P3.1, P3.2 or P3,3) using CH1 and
CH0 in the SAD SFR.
4.
Enter DC Compare mode by setting the ‘DC_COMP’
enable bit in the SADB SFR.
5.
Enable INT1 using the IE SFR.
6.
Enter Power-down/Idle mode. Upon wake-up, the
SAD should be restored to its conventional operating
mode by disabling the ‘DC_COMP’ control bit.
handbook, halfpage
MBK960
MUX
4 : 1
ADC0
ADC1
ADC2
ADC3
CH<1:0>
SAD<3:0>
SADB<3:0>
VDDP
VHI
8-BIT
DAC
Fig.11 SAD block diagram.
17 I
2
C-BUS SERIAL I/O
The I
2
C-bus consists of a serial data line (SDA) and a
serial clock line (SCL). The definition of the I
2
C-bus
protocol can be found in “The I
2
C-bus and how to use it
(including specification). Philips Semiconductors”.
The device operates in four modes:
Master transmitter
Master receiver
Slave transmitter
Slave receiver.
The microcontroller peripheral is controlled by the Serial
Control SFR (S1CON) and its status is indicated by the
Status SFR (S1STA). Information is transmitted/received
to/from the I
2
C-bus using the Data SFR (S1DAT). The
Slave Address SFR (S1ADR) is used to configure the
slave address of the peripheral.
The byte level I
2
C-bus serial port is identical to the I
2
C-bus
serial port on the P8xC558, except for the clock rate
selection bits CR<2:0>. The operation of the subsystem is
described in detail in the “P8xC558 data sheet”.
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