參數(shù)資料
型號(hào): SAA5647HL
廠商: NXP Semiconductors N.V.
英文描述: Enhanced TV microcontrollers with On-Screen Display (OSD)(帶全屏顯示的增強(qiáng)型TV控制器)
中文描述: 與微控制器在強(qiáng)化電視屏幕顯示(OSD)(帶全屏顯示的增強(qiáng)型電視控制器)
文件頁數(shù): 33/112頁
文件大小: 436K
代理商: SAA5647HL
2000 Jun 30
33
Philips Semiconductors
Objective specification
Enhanced TV microcontrollers with
On-Screen Display (OSD)
SAA56xx
Text Register 29 (TXT29)
TEN B
disable twist function for Page B (logic 0)
enable twist character set for Page B (logic 1)
twist character set selection for Page B
character code columns 8 and 9 defined as single plane characters for display
Page B (logic 0)
character code columns 8 and 9 defined as double plane characters (special
graphics characters) for display Page B (logic 1)
enable use of OSD LAN B<2:0> to define language option for display, instead of
C12/C13/C14 for display Page B
alternative C12/C13/C14 bits for use with OSD menus for display Page B
TS B1 to TS B0
OSD PLANES B
OSD LANG ENABLE B
OSD LAN B2 to OSD LAN B0
Text Register 30 (TXT30)
TC B2 to TC B0
BOTTOM/TOP B
language control bits (C12/C13/C14) that has twist character set for Page B
Display memory rows 0 to 11 when double height bit is set on display Page B
(logic 0)
Display memory rows 12 to 23 when double height bit is set on display Page B
(logic 1)
display each character as twice normal height on display Page B (logic 1)
Display memory row 24 information below Teletext page (on display row 24) on
display Page B (logic 0)
Display memory row 24 information above Teletext page (on display row 0) on
display Page B (logic 1)
display row 24 from basic page memory on display Page B (logic 0)
display row 24 from appropriate location in extension memory on display Page B
(logic 1)
display only row 24 on display Page B (logic 1)
DOUBLE HEIGHT B
STATUS ROW TOP B
DISLAY X24 B
DISPLAY STATUS ROW ONLY B
Text Register 31 (TXT31)
GPF11 to GPF10
general purpose register, bits defined by mask programmable location
(Character ROM address 09FEH)
00 = 80C51 configured for 6 MHz operation
01 = 80C51 configured for 12 MHz operation
10 = reserved
11 = 80C51 configured for 6 MHz operation
GPF9 to GPF8
Text Register 32 (TXT32)
9FE11
9FF11 to 9FF5
reserved
mask programmable bits available for UOC configuration (Character ROM
address 09FFH)
Text Register 33 (TXT33)
BFE7 to BFE0
mask programmable bits available for UOC configuration (Character ROM
address 0BFEH)
Text Register 34 (TXT34)
BFE11 to BFE8
mask programmable bits available for UOC configuration (Character ROM
address 0BFEH)
BITS
FUNCTION
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