參數(shù)資料
型號: SAA2502
廠商: NXP Semiconductors N.V.
英文描述: ISO/MPEG Audio Source Decoder
中文描述: 的ISO / MPEG音頻信源解碼器
文件頁數(shù): 8/64頁
文件大小: 318K
代理商: SAA2502
1997 Nov 17
8
Philips Semiconductors
Preliminary specification
ISO/MPEG Audio Source Decoder
SAA2502
7.2.1
E
XTERNAL SAMPLE CLOCK
In applications where a 256
×
f
s
sample clock is available,
the use of external crystals may be avoided by putting the
SAA2502 clock generator module in ‘external sample
clock mode’. Such mode setting may be realized by setting
control flag FSCINP of the control interface. In this event
the sample clock has to be provided to the FSCLKIN clock
input. If sample rate switching should be supported,
required clock frequency changes are the responsibility of
the application. After such a clock frequency change,
enforcement of a soft reset is advised.
In external sample clock mode (and only in that mode) the
clock generator module is able to accept a 384
×
f
s
sample
clock input. If that mode of operation is desired the control
flag FSC384 should be set.
The FSCLK output is normally disabled in this mode.
If enabled (by setting control flag FSCENA) FSCLK will
produce a buffered copy of FSCLKIN.
X22IN, X22OUT, REFCLK and PHDIF are not used in this
mode. X22IN and REFCLK should be connected to GND
or V
DD
.
MCLKIN is used to provide the (free running) master clock.
This may either be achieved by applying a correct clock
signal to MCLKIN or by connecting a crystal between
MCLKIN and MCLKOUT. In external sample clock mode
(and only in that mode) the master clock may deviate from
24.576 MHz. The master clock frequency value required
depends on the state of pin MCLK24 (see Table 2).
Table 2
Master clock frequency setting by MCLK24
7.2.2
F
REE RUNNING INTERNAL SAMPLE CLOCK
This is the default mode of operation: 256
×
f
s
for all six
supported sample rates is generated internally from the
clock frequencies supplied to MCLKIN (24.576 MHz) and
X22IN (22.5792 MHz) as shown in Table 3.
MCLK24
FREQUENCY
MINIMUM
256
×
f
s
MAXIMUM
GND
12.288 MHz
(256
×
48 kHz)
24.576 MHz
(512
×
48 kHz)
V
DD
512
×
f
s
Table 3
Internal sample clock (default mode)
Note
1.
Asymmetrical FSCLK.
The main advantage of this mode is that the SAA2502
determines automatically which sampling rate is active
from the sampling rate setting of the input data bit stream,
and then selects either MCLKIN or X22IN divided by the
correct number as the sample clock source.
Therefore this mode is particularly suited in applications
supporting dynamically varying sampling rates.
The required clocks may either be applied to MCLKIN
(respectively to X22IN) or be generated by connecting a
crystal between MCLKIN and MCLKOUT (respectively
between X22IN and X22OUT).
The recommended crystal oscillator configuration is
shown in Fig.3. The specified component values only
apply to crystals with a low equivalent series resistance
of <40
.
FSCLKIN, REFCLK and PHDIF are not used in this mode
(FSCLKIN and REFCLK should be connected to V
SS
or
V
DD
). MCLK24 has to be connected to V
DD
, while the
control flags FSCINP and FSC384 should be left in their
default (cleared) states. If the FSCLK output is enabled (by
setting control flag FSCENA) FSCLK will produce a
buffered version of 256
×
f
s
.
SAMPLE
FREQUENCY
256
×
48 kHz
RESULTANT FREQUENCIES
(MHz)
12.288
256
×
44.1 kHz
11.2896
256
×
32 kHz
8.192
(1)
256
×
24 kHz
6.144
256
×
22.05 kHz
5.6448
256
×
16 kHz
4.096
2
24.576
2
22.5792
3
24.576
4
24.576
4
22.5792
6
24.576
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