
1997 Nov 17
35
Philips Semiconductors
Preliminary specification
ISO/MPEG Audio Source Decoder
SAA2502
Table 30
 Explanation of bits in Table 29
Notes
1.
2.
Default settings (settings value after a hard reset).
The SAA2502 can only decode one of the dual channels, at a time. Both left and right audio outputs then play the
selected channel.
Table 31
 Sampling rate and bit rate: 1 byte (write-only, unrestricted type, local address = 1BH)
Table 32
 Soft reset: 1 byte (write-only, unrestricted type, local address = 1EH)
BIT
DESCRIPTION
SYMOD1 and SYMOD0
audio frame synchronization mode:
00
(1)
: general non-byte aligned frame synchronization
01: MPEG layer II non-byte aligned frame synchronization
10: byte aligned frame synchronization
11: sync pulse frame synchronization
input interface mode of operation:
00
(1)
: master input mode for static bit rates
01: slave input mode for static bit rates
10: buffer controlled input mode for static bit rates
11: buffer controlled input mode for variable bit rates
enable stop requesting flag:
0
(1)
: input requesting continues when STOP = logic 1
1: input requesting stops when STOP = logic 1
CRC presence:
0
(1)
: protection bit in the MPEG frame header is used to determine CRC presence
1: CRC is assumed be present by definition (the protection bit is overruled)
dual channel mode channel select (with other modes of input data = don’t care):
0
(1)
: select channel I
1: select channel II
enable scale factor CRC protection:
0
(1)
: no scale factor protection
1: scale factor CRC protection enabled
INMOD1 and INMOD0
STOPRQ
CRCACT
SELCH2
(2)
SFCRC
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SFX2
SFX1
SFX0
BRX4
BRX3
BRX2
BRX1
BRX0
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
0
0
0
0
0
0
0