1997 Nov 17
26
Philips Semiconductors
Preliminary specification
ISO/MPEG Audio Source Decoder
SAA2502
7.5.3
B
IT SERIAL ANALOG OUTPUT
In order to serve applications which require low to medium
performance stereo audio output, two bit serial analog
outputs are provided (one for each channel). The on-chip
DACs each consist of three functional blocks in series:
4
×
f
s
up-sampling filter
AC and DC dithering block
N
×
f
s
noise shaper; see Table 17.
Table 17
Value of N for N
×
f
s
noise shaper
MODE
SAMPLE
RATE
VALUES
External sample clock mode
FSC384 = 0
FSC384 = 1
N = 256
N = 384
N = 256
N = 256
N = 384
N = 512
Other clock generator modes f
s
= 48 kHz
f
s
= 44.1 kHz
f
s
= 32 kHz
f
s
= 24 kHz
f
s
= 22.05 kHz N = 512
f
s
= 16 kHz
N = 768
The two analog outputs deliver a ‘pulse density modulated’
signal, switching between REFN and REFP. The format is
programmable (through the control interface):
Non return-to-zero format (subsequent logic 1 pulses
are merged)
Return-to-zero format (subsequent logic 1 pulses are
separated by logic 0 levels).
The quality of the analog output signal depends on several
external factors:
Stability and decoupling of the analog supply
Absence of jitter on the sample clock
Which external low-pass filter circuit is used
The layout of the low-pass filter.
The recommended external low-pass filter is shown in
Fig.17. With this circuit the DACs performance is <
75 dB
(THD + N)/S with a 1 kHz sine wave, measured over the
bandwidth 20 Hz to 20 kHz. The amplifier in the low-pass
filter circuit is the Class AB stereo headphone driver
TDA1308.
The recommended DAC output format is non
return-to-zero, this has a better signal-to-noise ratio than
the return-to-zero format.
Fig.16 Bit serial output formats.
handbook, full pagewidth
MGE481
LFTPOS
RGTPOS
LFTNEG
RGTNEG
bit serial data
0
1
1
0
0
1
0
1
1
0
0
1
non-return-to-zero
(recommended)
return-to-zero