參數(shù)資料
型號(hào)： SAA2502
廠商： NXP Semiconductors N.V.
英文描述： ISO/MPEG Audio Source Decoder
中文描述： 的ISO / MPEG音頻信源解碼器
文件頁(yè)數(shù)： 7/64頁(yè)
文件大小： 318K
代理商： SAA2502
1997 Nov 17
7
Philips Semiconductors
Preliminary specification
ISO/MPEG Audio Source Decoder
SAA2502
7
FUNCTIONAL DESCRIPTION
7.1
Basic functionality
From a functional point of view, several blocks can be
distinguished in the SAA2502. A clock generator section
derives the internally and externally required clock signals
from its clock inputs. The input interface section receives
or requests coded input data in one of the supported input
interface modes. The demultiplexer processor handles
frame synchronization, parsing, demultiplexing and error
concealment of the input data stream The de-quantization
and scaling processor performs the transformation and
scaling operations on the (demultiplexed) coded sample
representations in the input bitstream to yield sub-band
domain samples.
The sub-band samples are transferred to the synthesis
sub-band filter bank processor which reconstructs the
baseband audio samples. The output interface block
transforms the audio samples to the output formats
required by the different output ports.
The decoding control block houses the I
2
C-bus/L3
microcontroller interface, and handles the response to
external control signals. This section enables the
application to configure the SAA2502, to read its decoding
status, to read ancillary data and so on.
Several pins are reserved for boundary scan test (5 pins)
and factory test scan chain control (2 pins).
7.2
Clock generator module
The SAA2502 clock interfacing is designed for application
versatility. It consists of 9 signals (see Table 1).
The clock generator provides the following clock signals:
Internal sample clocks
External buffered sample clock FSCLK
Processor master clock
Coded input data bit clock
Coded input data request clock
The module can be configured to operate in 3 different
modes of operation:
External sample clock mode
Free running internal sample clock mode
Locked internal sample clock mode.
Clock generator operation mode must be stationary while
the device is in normal operation. Changing mode should
always be followed by a (soft) reset.
f
32
input bit rate
=
Table 1
Clock interfacing signals
SIGNAL
DIRECTION
FUNCTION
MCLKIN
MCLKOUT
MCLK24
X22IN
X22OUT
FSCLKIN
FSCLK
REFCLK
PHDIF
input
output
input
input
output
input
output
input
output
master clock oscillator input or signal input
master clock oscillator output
master clock frequency indication
22.5792 MHz clock oscillator input or signal input
22.5792 MHz clock oscillator output
external sample rate clock signal input
sample rate clock signal output
coded input data rate reference clock
phase difference indication output between reference clock and sample clock
相關(guān)PDF資料
PDF描述
SAA2502H ISO/MPEG Audio Source Decoder
SAA2503 MPEG2 audio decoder(MPEG2 音頻譯碼器)
SAA2503HT MPEG2 audio decoder
SAA2505H-M1 Digital multi-channel audio IC DUET
SAA2505 Digital multi-channel audio IC DUET
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SAA2502H 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:ISO/MPEG Audio Source Decoder
SAA2503 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:MPEG2 audio decoder
SAA2503HT 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:MPEG2 audio decoder
SAA2505 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital multi-channel audio IC DUET
SAA2505H 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital multi-channel audio IC DUET
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